Tunnel field-effect transistor (FET) is a promising candidate in ultralow-power applications due to its distinct operation mechanism, namely band-to-band tunneling (BTBT). The integration of different low-bandgap materials is explored extensively to improve the ON-state BTBT current of the tunnel FETs. The epitaxial tunnel layer (ETL) tunnel FET integrated with the hetero-material system is a promising structure due to its process compatibility with CMOS technologies. In the scenario of n-channel operation, the concept of the suppression of the low electric field BTBT is proposed. The SiGe/Si hetero-material system is applied to the n-channel ETL tunnel FET to suppress the low electric field BTBT by the ETL band engineering. The optimized ETL tunnel FET exhibits a high ON-state BTBT current due to the low bandgap material in the ETL. The average SS behavior is also further improved by suppressing the low electric field BTBT. In this study, the design concept and the device parameters of the n-channel ETL tunnel FET are discussed in detail. The performances of the complementary ETL tunnel FETs using the SiGe/Si hetero-material system are also provided to enrich the value of the ETL tunnel FET in the circuit applications.

Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET Structure

A CMOS process compatible p-channel tunnel field-effect transistor (TFET) with an epitaxial tunnel layer (ETL) structure is demonstrated experimentally. The fabricated ETL p-TFET exhibits high tunneling current ( $I_{\mathrm{\scriptscriptstyle ON}}\sim 0.17~\mu \text{A}/\mu \text{m}$ at $\vert V_{G}\vert =0.5$ V after $V_{\mathrm {TH}}$ adjustment), ultra-low OFF-state current, and good average subthreshold swing (S.S. $\sim 100$ mV/ decade up to 10 nA/ $\mu \text{m}$ ). Overall performance exceeds that of the current state-of-the-art Ge-based planar p-TFETs.

Experimental Demonstration of p-Channel Germanium Epitaxial Tunnel Layer (ETL) Tunnel FET With High Tunneling Current and High ON/OFF Ratio

Study of novel junctionless Ge n-Tunneling Field-Effect Transistors with lightly doped drain (LDD) region

In this paper, we analyze the heterojunction GaAs 0.4 Sb 0.6 /In 0.65 Ga 0.35 As TFET with vertical nanowire structure and non-uniform diameter design (V-NW TFET with non-uniform diameter). A thin channel layer (Ti) is inserted between the gate and source regions for improving the on currents, and the non-uniform diameter thickness is used for suppressing the leakage current (Imin). The bandgap widening induced by quantum confinement is considered in this work. The leakage current can be suppressed by using thinner diameter thickness of the drain/channel junction (Tdc), and the gate-to-drain underlap design is used to further reduce the ambipolar leakage. The impacts of Ti, Tdc, source and drain doping concentrations, and gate-to-source overlap length (Lovs) on the V-NW TFET have been investigated. Compared with the ultra-thin body (UTB) TFET, the proposed V-NW TFET with non-uniform diameter (thin Tdc) exhibits 2 times larger Ion (236 μA/μm) due to the increased line tunneling area, and 59.8 times lower leakage current (5.5 × IO−10 μA/μm).

Device design of vertical nanowire III-V heterojunction TFETs for performance enhancement

An enhanced tunnel field effect transistor includes a substrate, a layer of P-I-N structure, a hetero-material layer, a gate dielectric layer, a gate structure and a spacer, in which the layer of P-I-N structure is disposed on the substrate, the hetero-material layer is disposed on portion of the layer of P-I-N structure, the gate dielectric layer is disposed on the hetero-material layer, the gate structure is disposed the gate dielectric layer and a spacer is disposed on a sidewall of the hetero-material layer, the gate dielectric layer, and the gate structure. The hetero-material layer can increase the tunneling efficiency of the enhanced tunnel field effect transistor to increase the conductor current to improve the enhanced tunnel field effect transistor performance.

https://ir.nctu.edu.tw:443/bitstream/11536/104337/1/08853824.pdf

Enhanced tunnel field effect transistor

Epitaxial Tunnel Layer Structure for Complementary Tunnel FETs Enhancement

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Epitaxial Tunnel Layer Structure for Complementary Tunnel FETs Enhancement