A data-driven multiprocessor architecture for the rapid prototyping of complex DSP algorithms, based on direct execution of data-flow graphs, is presented. High computation bandwidth is achieved by exploiting the fine-grain parallelism inherent in the target algorithms using simple processing elements called nanoprocessors interconnected by a configurable static communication network. The use of distributed control and the data-driven execution approach resulted in a highly scalable and modular architecture. A prototype chip, which is currently being designed, contains 64 nanoprocessors, 1 kByte of memory in four banks and eight 16-bit I/O ports, and provides 3.2 GOPS peak when running at 50 MHz. The benchmark results, based on a variety of DSP algorithms in video processing, digital communication, digital filtering and speech recognition, confirm the performance efficiency and generality of the architecture. >

A reconfigurable data-driven multiprocessor architecture for rapid prototyping of high throughput DSP algorithms

A synthesis system called HYPER is proposed for real-time applications. HYPER takes a flow graph description of an algorithm as the input and performs scheduling, resource allocation, optimizations, and transformations. A dedicated bit-sliced data path cluster is generated by the system and the layouts can be further generated through the LAGER IV system. >

/pdf/hyper-an-interactive-synthesis-environment-for-high-3wf34boywj.pdf

HYPER: an interactive synthesis environment for high performance real time applications

The Ring Array Processor: a multiprocessing peripheral for connectionist applications

The high throughput (computation) requirements of real-time digital signal processing (scDSP) systems usually dictate hardware intensive solutions. Often attendant to hardware approaches are problems of high development costs, slow turnaround, susceptibility to errors, and difficulty in testing and debugging, all of which tend to inhibit the rapid implementation of such systems. Research is underway into the synthesis of application specific hardware to aid the system designer by automatically generating hardware that is "correct by construction". The creation of configurable, pre-fabricated hardware that has been designed for high speed computations forms part of this research and is the main topic of this thesis.
This work contains a survey of some typical real-time scDSP algorithms drawn from video and speech processing and summarizes the particular computation challenges posed by this class of algorithms. Currently available hardware choices and their trade-offs and limitations are discussed. A multiprocessor architecture consisting of programmable arithmetic devices is presented as a novel platform for supporting high speed digital signal processing. The scVLSI realization of the architecture and an accompanying software development environment are presented as a proof of concept. The main conclusion of this work is that software-configurable hardware approaches to high speed digital signal processing problems form viable alternatives to existing approaches, for systems designers interested in rapidly prototyping or implementing their ideas.

Programmable arithmetic devices for high speed digital signal processing

A data-driven multiprocessor architecture called PADDI-2 specially designed for rapid prototyping of high throughput digital signal processing algorithms is presented. Characteristics of typical high speed DSP systems were examined and the efficiencies and deficiencies of existing traditional architectures were studied to establish the architectural requirements, and to guide the architectural design. The proposed PADDI-2 architecture is a highly scalable and modular, multiple-instruction stream multiple-data stream (MIMD) architecture. It consists of a large number of fine-grain processing elements called nanoprocessors interconnected by a flexible and high-bandwidth communication network. The basic idea is that a data flow graph representing a DSP algorithm is directly mapped onto a network of nanoprocessors. The algorithm is executed by the nanoprocessors executing the operations associated with the assigned data flow nodes in a data-driven manner. High computation power is achieved by using multiple nanoprocessors to exploit the large amount of fine-grain parallelism inherent in the target algorithms. Programming flexibility is provided by the MIMD control strategy and the flexible interconnection network which can be reconfigured to handle a wide range of DSP algorithms, including those with heterogeneous communication patterns.
As a proof of concept, a single-chip multiprocessor integrated circuit containing 48 16-bit nanoprocessors was designed and fabricated in a 2-metal 1-$\mu$m CMOS technology. A 2-level, area-efficient communication network occupying only 17% of the core area provides flexible and high-bandwidth inter-processor communications. Running at 50 MHz, the chip achieves 2.4 GOPS peak performance and 800 MBytes per second I/O bandwidth. An integrated development system including an assembler, a VHDL-base system simulator, and a demonstration board has been developed for PADDI-2 program development and demonstration.
The benchmark results based on a variety of DSP algorithms in video processing, digital communication, digital filtering, and speech recognition confirm the performance, efficiency and generality of the architecture. Moreover, when compared with several competitive architectures that target the same application domain, PADDI-2 is in general about 2 to 3 times better in terms of hardware efficiency.

A data-driven multiprocessor architecture for high throughput digital signal processing

A system architecture has been developed to implement real-time large-vocabulary continuous-speech recognition using HMM (hidden Markov model) algorithms and bigram language models. It is shown that the largest bottleneck in such a system is located in the memory access. The architecture exploits a variety of techniques, such as partitioning and replication, to cope with this memory bottleneck. The required throughput is achieved with the aid of extensive pipelining (up to thirteen levels deep) and concurrency. The architecture allows extension to larger vocabularies by the addition of more parallel units. Pin count considerations have resulted in the definition of five custom integrated circuits which are currently being tested. Using the proposed approach, the authors are currently designing and debugging a real-time 3000-word continuous-speech recognition system that uses bigram language models. >

A large-vocabulary real-time continuous-speech recognition system

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A large-vocabulary real-time continuous-speech recognition system