The paper extends the concept of justification to the context of Answer Set Programming---a recent paradigm that builds on the foundations of logic programming, answer set semantics, and non-monotonic reasoning. A justification describes the support for the truth value of each atom in an answer set of a logic program, and it can be employed as a tool for reasoning and debugging of answer set programs. The paper describes the implementation of the notion of justification in the ASP system along with some examples of its applications.

Justification and debugging of answer set programs in ASP

Embedded systems are becoming increasingly common in our everyday lives. As technology progresses, these systems become more and more complex, and designers handle this increasing complexity by reusing existing components (Intellectual Property blocks). At the same time, the systems must fulfill strict requirements on reliability and correctness.

This paper proposes a formal verification methodology which smoothly integrates with component-based system-level design using a divide and conquer approach. The methodology assumes that the system consists of several reusable components, each of them already formally verified by their designers. The components are considered correct given that the environment satisfies certain properties imposed by the component. The methodology verifies the correctness of the glue logic inserted between the components and the interaction of the components through the glue logic. Each such glue logic is verified one at a time using model checking techniques.

Experimental results have shown the efficiency of the proposed methodology and demonstrated that it is feasible to apply such a verification methodology on real-life examples.

/pdf/formal-verification-of-component-based-designs-58q27sgq03.pdf

Formal verification of component-based designs

Component reuse techniques have been a recent focus of research because they are seen as the next-generation techniques to handle increasing system complexities. However, there are several unresolved issues to be addressed and prominent among them is the issue of component matching. As the number of reusable components in a component database grows, the task of manually matching a component to the user requirements becomes infeasible. Automating this matching can help in rapid system prototyping, improving quality and reducing cost. In addition, if the matching algorithm is sound, this approach can also reduce precious validation effort.In this article, we propose an algorithm for automatic matching of a design function to a device from a component database. The distinguishing feature of the algorithm is that when successful, it generates an interface that can automatically adapt the device to behave as the function. The algorithm is based on a new simulation relation called forced simulation that is shown to be a necessary and sufficient condition for component matching to be possible for a given pair of function and device. We demonstrate the application of the algorithm by reusing on some programmable components of the Intel family.

Forced simulation: A technique for automating component reuse in embedded systems

In the current very deep submicron technology era, fault tolerant mechanisms perform an essential function to cope with the effects of soft errors. To evaluate the effectiveness of the fault tolerant mechanism, reliability engineers use simulated fault injections using either saboteur modules or mutants in the simulation model. However, the two methods suffer from both inefficiency in the simulation mechanism and difficulties with the experimental setups. To overcome these inefficiencies, we propose the Verilog-based simulated fault injection (VFI) technique. VFI has the following advantages. First, modification of the design model is unnecessary. Second, the fault injection simulation procedure is simple and efficient. Third, various types of fault injection experiments can be performed. To evaluate the effectiveness of the proposed methodology, we developed a VFI environment using the ICARUS Verilog Simulator. From the experimental results, we were able to qualitatively evaluate the reliability of the target simulation models and to assess the effectiveness of the employed fault-tolerance mechanisms.

https://onlinelibrary.wiley.com/doi/pdf/10.4218/etrij.11.0110.0106

Simulated Fault Injection Using Simulator Modification Technique

Because of tight power and energy constraints, industry is progressively shifting toward heterogeneous system-on-chip (SoC) architectures composed of a mix of general-purpose cores along with a number of accelerators. However, such SoC architectures can be very challenging to efficiently program for the vast majority of programmers, due to numerous programming approaches and languages. Libraries, on the other hand, provide a simple way to let programmers take advantage of complex architectures, which does not require programmers to acquire new accelerator-specific or domain-specific languages. Increasingly, library-based, also called algorithm-centric, programming approaches propose to generalize the usage of libraries and to compose programs around these libraries, instead of using libraries as mere complements.In this article, we present a software framework for achieving performance portability by leveraging a generalized library-based approach. Inspired by the notion of a component, as employed in software engineering and HW/SW codesign, we advocate nonexpert programmers to write simple wrapper code around existing libraries to provide simple but necessary semantic information to the runtime. To achieve performance portability, the runtime employs machine learning (simulated annealing) to select the most appropriate accelerator and its parameters for a given algorithm. This selection factors in the possibly complex composition of algorithms used in the application, the communication among the various accelerators, and the tradeoff between different objectives (i.e., accuracy, performance, and energy).Using a set of benchmarks run on a real heterogeneous SoC composed of a multicore processor and a GPU, we show that the runtime overhead is fairly small at 5.1p for the GPU and 6.4p for the multi-core. We then apply our accelerator selection approach to a simulated SoC platform containing multiple inexact accelerators. We show that accelerator selection together with hardware parameter tuning achieves an average 46.2p energy reduction and a speedup of 2.1× while meeting the desired application error target.

/pdf/performance-portability-across-heterogeneous-socs-using-a-302tryk73u.pdf

Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach

Application of Cfsmcharts for Modelling Real-Time and Industrial Embedded Systems

Component-based synthesis of embedded systems will lead to the reuse of a vast library of hardware and software components and also facilitate rapid prototyping. However it is still low key, a primary reason being the lack of a systematic attempt at the development of automatic component matching algorithms. The main task of such an algorithm is to map a design function to a device from a library of system-level components. In this paper we propose a novel notion of simulation called forced simulation to formalize the correspondence between a function and a device. What distinguishes forced simulation from other techniques is the idea of forcing via an external interface, which can be automatically synthesized, and is useful for adapting the system level component to the given design functionality. We propose a new component matching algorithm based enforced simulation and illustrate it via the example of mapping a lathe controller port to Intel 82C55 in mode 2.

Automatic component matching using forced simulation

Synchronous languages may be used for specification and design of embedded systems Assuming the availability of a library of synchronous programs, we propose a technique to enable reuse of these programs, via an algorithm for automatic matching of a design function to a program from the library The algorithm, when successful, generates an interface which automatically adapts the program The algorithm is based on a new simulation relation called synchronous forced simulation, which is shown to be necessary and sufficient for matching a given pair of function and program

A formal approach to component based development of synchronous programs

Embedded systems are application specific digital systems that are usually designed using a microprocessor, along with a set of programmable hardware and software components. Since these systems are real time in nature, specification of temporal constraints is a key issue. We have recently proposed the CFSMcharts language for component based specification of these systems. However this proposal had no features to specify quantitative temporal constraints that are crucial to embedded system specification. We propose a new model of time, called hidden time, for specification of temporal constraints in CFSMcharts and contrast it with existing schemes. The proposed scheme is hierarchical and hides away the quantitative temporal constraints from the top level specification. This leads to a simpler style for the specification of these constraints and simpler semantics for the top level specification. Another major contribution of the proposed scheme is that properties to be verified can be expressed in propositional temporal logic, whereas all the existing schemes have to use first order temporal logic. We also propose a new temporal logic called Hidden Propositional Temporal Logic (HPTL) as a requirement specification language. HPTL is based on the hidden time model and also supports module name qualifiers, which have applicability in a component based framework. Finally, we propose a scheme for automated verification.

Hidden time model for specification and verification of embedded systems

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