This special session on 3D TSVpsilas will highlight some of the fabrication processes and used technologies to create vias from the frontside of an active circuit to its backside and potential implementation solutions to form complex systems leveraging these novel possibilities. General techniques for via formation are discussed as well as advanced integration solutions leveraging the power of 3D TSVpsilas.

Through silicon vias as enablers for 3D systems

In the three-dimensional integration of integrated circuits, a thinned semiconductor substrate is arranged on a second semiconductor substrate and is mechanically and electrically connected thereto. To that end, in the second, thinned semiconductor substrate, continuous contact holes are formed proceeding from a substrate rear side as far as a first metal wiring plane on a substrate front side. In order to align the contact holes with the structures arranged on the front side, a structure is arranged on the front side of the substrate, which can be used as an alignment mark on the front side. The structure is overgrown with a useful layer and uncovered proceeding from the rear side of the substrate, so that the structure can also be used as an alignment mark from the rear side. This avoids an alignment error between the structures arranged on the front side and the rear side.

Method for aligning structures on a semiconductor substrate

This special session on 3D TSV's will highlight some of the fabrication processes and used technologies to create vias from the frontside of an active circuit to its backside and potential implementation solutions to form complex systems leveraging these novel possibilities. General techniques for via formation are discussed as well as advanced integration solutions leveraging the power of 3D TSV's.

Through Silicon Vias as Enablers for 3D Systems

The technology to realize Vertically Integrated Circuits (VIC) utilizing interchip vias for the electrical interchip connection in a wafer stack was developed To achieve this advanced 3D integration technology the designated top wafers in the wafer stack were thinned down to 10μm and glued onto the planarized bottom wafers. The realization of the interchip via concept providing vias through the thinned top wafer required the development of plasma etching processes with minimized RIE lags for dielectrics, single crystal silicon, and for the interchip glue layer as well as of extremely highly conformal deposition processes for dielectrics for lateral electrical via isolation with a double dielectric spacer technique and for TiN and W to realize the vertical interchip metallization by void free via refill applying a high aspect ratio W plug technique. The developed technology utilizes CMOS compatible processes exclusively and requires no wafer backside processes.

Vertically integrated circuits : A key technology for future high performance systems

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Vertically integrated circuits : A key technology for future high performance systems