Using a novel process flow, we managed to cointegrate several devices on the same wafer; single gate (SG), ground plane (GP), perfectly aligned double gate (DG), misaligned DG and oversized back-gate DG. This paper reports the experimental evaluation of the gate architectures influence on the performance of silicon-on-insulator MOSFETs. DG MOSFETs, with gate lengths down to 40 nm, are experimentally compared to SG and GP MOSFETs. Short-channel effect (SCE) control, static performance and mobility are quantified for each architecture. When compared to SG and GP transistors, the DG transistor shows the best SCE control and performance as predicted by simulations. Gate coupling is demonstrated to be a sensitive and a nondestructive method to evaluate the real on-wafer alignment. Using this method, we report an experimental analysis of gate misalignment influence on DG MOSFETs' performance and SCE. It is found that misalignment primarily affects the subthreshold parameters due to an electrostatic control loss. The DG MOSFET with a slightly oversized back gate (10 nm on each side of the top gate) is a promising solution, if a 10% loss in dynamic performance can be tolerated.

Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance

Accurate Determination of Transport Parameters in Sub‐65 nm MOS Transistors

For the first time, we report an experimental comparison between planar double gate, single gate and ground plane CMOSFETs. Thanks to an original process, we managed to co-integrate, on the same wafer, these three devices with a TiN metal gate. Short channel effect control, static performance and mobility are quantified for each architecture. The advantages of double gate devices over ground plane and single gate transistors are experimentally highlighted. Ground plane MOSFETs require an optimized BOX in order to achieve a 30% in the saturation current.

Experimental comparison between double gate, ground plane, and single gate SOI CMOSFETs

La miniaturisation des composants electroniques qui permet aujourd'hui une integration a grande echelle a ete possible grâce aux innovations des procedes de fabrication. Ces modifications affectent profondement le comportement electrique des transistors MOS lorsque la longueur de grille devient inferieure a 100nm, alterant notre comprehension physique de ce dispositif. Ce travail de these se situe dans le domaine de l'etude des performances des transistors fabriques dans les filieres avancees (technologies sub-45nm) et l'analyse de leur reponse electrique. Il propose d'ameliorer les methodologies existantes et apporte de nouvelles techniques d'extraction qui permettent une analyse des parametres electriques valide dans un environnement industriel, sur des transistors courts. L'utilisation des ces nouvelles techniques permet une comprehension physique plus juste, utile pour predire les performances des technologies futures.

https://tel.archives-ouvertes.fr/tel-00461948/document

Contribution à l'étude expérimentale du transport dans les transistors de dimensions déca-nanométriques des technologies CMOS sub 45nm

In this work, we use the modified McLarty function to understand and extract accumulation (μacc) and bulk (μbulk) mobility in Double Gate (DG) Junctionless (JL) MOSFETs over a wide range of doping concentration (Nd) and temperature range (250 K to 520 K). The approach enables the estimation of mobility and its attenuation factors (θ1 and θ2) by a single method. The extracted results indicate that μacc can reach higher values than μbulk due to the screening effect. Results also show that θ2 extracted in the accumulation regime of JL transistors exhibit relatively low values in comparison to inversion and accumulation mode devices. It is shown that the attenuation factor (θ1) in JL devices designed with higher Nd (≥1019 cm−3) is mainly affected by series resistance (Rsd) whereas, in inversion mode (IM) and Accumulation mode (AM) devices, θ1 factor is governed by both the intrinsic mobility reduction factor (θ10) and Rsd. Additionally, the impact of variation in oxide thickness (Tox), gate length (Lg), Nd and temperature on θ1 and θ2 has been investigated for JL transistor. The weak dependence of μbulk and μacc on temperature shows the prevalence of coulomb scattering over phonon scattering for heavily doped JL transistors. The work provides insights into different modes of operation, extraction of mobility and attenuation factors which will be useful for the development of compact models for JL transistors.

https://iopscience.iop.org/article/10.1088/1361-6641/aa92ff/pdf

Extraction of mobility and Degradation coefficients in double gate junctionless transistors

Parameter extraction stands as a critical issue for the modeling, simulation and design of CMOS transistors and circuits. Over the years, many methods have been proposed, refined and optimized until they became unable to account for new device characteristics brought about by technological progress. Such a situation applies to ultra-thin oxides, where the transconductance may exhibit negative values. The aim of this paper is: (1) to propose an adequate method for the extraction of the threshold voltage V/sub T/, field effect mobility /spl mu//sub 0/, effective channel length (L-/spl Delta/L), gate-induced mobility attenuation factors /spl theta//sub 1,2/; and (2) to demonstrate its superiority over standard techniques used in thicker oxides (>10 nm). Our test devices were n-channel (partially and fully depleted) SOI MOSFET's with silicon thicknesses ranging from 30 to 150 nm, with LDD configuration and various gate oxides from 4.5 to 17.5 nm thick. The device width was 25 /spl mu/m and the gate length varied from 0.4 to 25 /spl mu/m.

http://ieeexplore.ieee.org/iel2/3915/11345/00514207.pdf

A new parameter extraction method for ultra-thin oxide SOI MOSFET's

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A new parameter extraction method for ultra-thin oxide SOI MOSFET's