Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore’s law (i.e. More Moore) and More than Moore scaling. © The Author(s) 2014. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. [DOI: 10.1149/2.0051501jss] All rights reserved.

https://iopscience.iop.org/article/10.1149/2.0051501jss/pdf

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

JSS FOCUS ISSUE ON ADVANCED INTERCONNECTS :M ATERIALS ,P ROCESSING, AND RELIABILITY Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

The barrier layer in Cu technology is essential to prevent Cu from diffusing into the dielectric layer at high temperatures; therefore, it must have a high stability and good adhesion to both Cu and the dielectric layer. In the past three decades, tantalum/tantalum nitride (Ta/TaN) has been widely used as an inter-layer to separate the dielectric layer and the Cu. However, to fulfill the demand for continuous down-scaling of the Cu technology node, traditional materials and technical processes are being challenged. Direct electrochemical deposition of Cu on top of Ta/TaN is not realistic, due to its high resistivity. Therefore, pre-deposition of a Cu seed layer by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is necessary, but the non-uniformity of the Cu seed layer has a devastating effect on the defect-free fill of modern sub-20 or even sub-10 nm Cu technology nodes. New Cu diffusion barrier materials having ultra-thin size, high resistivity and stability are needed for the successful super-fill of trenches at the nanometer scale. In this review, we briefly summarize recent advances in the development of Cu diffusion-proof materials, including metals, metal alloys, self-assembled molecular layers (SAMs), two-dimensional (2D) materials and high-entropy alloys (HEAs). Also, challenges are highlighted and future research directions are suggested.

Recent Advances in Barrier Layer of Cu Interconnects

Effect of deposition and annealing temperature on mechanical properties of TaN film

https://iopscience.iop.org/article/10.1149/2.0281901jes/pdf

Review—Ruthenium as Diffusion Barrier Layer in Electronic Interconnects: Current Literature with a Focus on Electrochemical Deposition Methods

Comparative investigation of TaN and SiCN barrier layer for Cu/ultra low k integration

Ta/SiCN bilayer barrier for Cu–ultra low k integration

This paper reports the effect of a flash copper layer, sandwiched between a copper film deposited by metal-organic chemical vapor deposition (MOCVD) and a TaN barrier metal, on copper diffusion through TaN barrier to Si substrate after rapid thermal annealing at different temperatures. It is found that for the structure of CVD Cu/TaN/SiO2/Si, which has no flash Cu layer, Cu could diffuse through the 25-nm-thick TaN barrier layer at an annealing temperature of 600°Cfor 180 s. However, by incorporating a flash Cu layer between the CVD Cu film and the TaN barrier, Cu diffusion can be significantly reduced. In addition to Cu, the out-diffusion of Si and oxygen, and the interaction between them can also be reduced by the incorporated flash Cu layer, due likely to the change of the crystallographic orientation of the CVD Cu films.

STUDY OF Cu DIFFUSION IN Cu/TaN/SiO2/Si MULTILAYER STRUCTURES

Characterization of Cu/Ta/ultra low-k porous polymer structures for multilevel interconnects

Two kinds of barrier layers, Ta and TaN, deposited on an ultra low k dielectric porous polymer film with k=2.3 were evaluated using various techniques after thermal treatments at 400°C for different periods of time. It was found that the sheet resistance of the Ta barrier increased significantly after being annealed for 60 min while that of TaN increased after 120 min due to Ta-O compound formation as revealed by X-ray diffraction and secondary ion mass spectrometry. The better integrity of the TaN compared Ta is due to N incorporation, which limits the diffusion of Ta and O. The diffusion coefficient of Ta in the porous polymer is 0.023±0.001 nm2/s, while the diffusion coefficient of TaN is only 0.0033±0.0001 nm2/s.

COMPARATIVE STUDY OF Ta AND TaN(N) IN THE BARRIER/ULTRA LOW k STRUCTURES FOR DEEP SUBMICRON INTEGRATED CIRCUITS

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