We present for the first time Si-doped HfO 2 -based OxRAM 16kbit arrays integrated in the BEOL of 28nm FDSOI CMOS, targeting low cost and low power embedded applications. Excellent LRS/HRS raw distributions are reported on 1T-1R 16kbit arrays with zero bit-fail up to 105 cycles, using core logic (GO1) selector transistors. The OxRAM compatibility with GO1 transistors paves the way to arrays with minimum bitcell area of $0.066\ \mu \mathrm{m}^{2}$ at $125\mu \mathrm{A}$ programming current. We also demonstrate direct correlation between transistor compliance current variability within the 1T-1R array and the LRS distribution. This result indicates that the intrinsic LRS variability is smaller than the measured one. SPICE Monte-Carlo simulations confirm the large compliance current dispersion measured on transistors designed at minimum gate length and show path to improve even further the LRS distribution and hence the OxRAM memory window.

16kbit 1T1R OxRAM arrays embedded in 28nm FDSOI technology demonstrating low BER, high endurance, and compatibility with core logic transistors

We report an experimental pFET with 420GHz f T , which to the best of our knowledge is the highest value reported for a silicon pFET. The transconductance is 1800uS/um. The technology is fully depleted silicon on insulator (FDSOI) with the pFET channel formed by SiGe condensation. This outstanding performance is achieved by a combination of layout and process optimization which minimizes capacitance and maximizes compressive strain on the channel. The technology features a high-k metal gate and short gate length (20nm drawn) in addition to the SiGe channel for high mobility.

RF-pFET in fully depleted SOI demonstrates 420 GHz F T

At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La2O3 as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters’ variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (Vth) of −0.289 V ± 12.7% and Ioff of less than 10−7 A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO2 formation at the Si interface and rapid annealing processing are required to achieve La2O3 thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on Vth, Ion and Ioff were investigated. The improved voltage scaling resulting from the lower Vth value is associated with the increased Ioff due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process.

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length.

X-ray irradiation-induced degradation in Hf0.5Zr0.5O2 fully depleted silicon-on-insulator n-type metal oxide semiconductor field-effect transistors

In this work we revisited the 22nm FDSOI technology for lowest power IoT, RF and mmWave applications. Ultra-low leakage and power devices are described, as part of the 22FDX® portfolio. Transistors performance is presented. N-FET (p-FET) drive current of 910μA/μm (856μA/μm) at 0.8V and 100pA/μm Ioff are reported fulfilling the requirements for ultra-low power and leakage design space. Excellent low noise is shown due to the suppressed RDF coming from the un-doped silicon channel. Superior fT and fmax have been measured on CMOS and LDMOS devices. 347GHz n-FET fT and 371GHz fmax were achieved on thin oxide CMOS devices. Simple PA circuit results are reported to highlight the benefit of 22FDX® technology for RF and mmWave applications. In conclusion, an outlook of the scalability as well as novel process integrations are discussed.

/pdf/22fdx-technologies-for-ultra-low-power-iot-rf-and-mmwave-1yosdtaaza.pdf

22FDX® Technologies for Ultra-Low Power IoT, RF and mmWave Applications

High-k metal gate (HKMG) has been implemented in production for nearly 10 years. As scaling of HKMG on bulk Si is reaching its limit, alternative device architecture such as FINFETs and FDSOI are being pursued. FDSOI is well suited for applications needing a balanced trade-off among power, performance and cost, such as the Internet of Things (IoTs). Here we show that compared to HKMG on bulk Si, HKMG FDSOI transistors have less VT variation due to its undoped channel. Furthermore, FDSOI unique back-biasing capability offers additional knob to further reduce VT variation. There are, however, a few challenges that must be overcome for successful integration of FDSOI in CMOS. Those challenges such as preventing thin SOI channel erosion, maintaining strain in channel SiGe, preventing oxygen ingress in gatestack, obtaining a low overlap capacitance and growing raised source/drain epi will be discussed.

Extending HKMG scaling on CMOS with FDSOI: Advantages and integration challenges

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Extending HKMG scaling on CMOS with FDSOI: Advantages and integration challenges