Giant energy storage and power density negative capacitance superlattices.

A neuromorphic system is composed of hardware-based artificial neurons and synaptic devices, designed to improve the efficiency of neural computations inspired by energy-efficient and parallel operations of the biological nervous system. A synaptic device-based array can compute vector–matrix multiplication (VMM) with given input voltage signals, as a non-volatile memory device stores the weight information of the neural network in the form of conductance or capacitance. However, unlike software-based neural networks, the neuromorphic system unavoidably exhibits non-ideal characteristics that can have an adverse impact on overall system performance. In this study, the characteristics required for synaptic devices and their importance are discussed, depending on the targeted application. We categorize synaptic devices into two types: conductance-based and capacitance-based, and thoroughly explore the operations and characteristics of each device. The array structure according to the device structure and the VMM operation mechanism of each structure are analyzed, including recent advances in array-level implementation of synaptic devices. Furthermore, we reviewed studies to minimize the effect of hardware non-idealities, which degrades the performance of hardware neural networks. These studies introduce techniques in hardware and signal engineering, as well as software-hardware co-optimization, to address these non-idealities through compensation approaches.

A comprehensive review of advanced trends: from artificial synapses to neuromorphic systems with consideration of non-ideal effects

Abstract This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate machine learning (ML) workloads. We conducted an exploration of device fabrication and proposed system-algorithm co-design to boost performance. A novel FeCap device, incorporating an interfacial layer (IL) and $$\text {Hf}_{0.5}\text {Zr}_{0.5}\text {O}_2$$ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"> <mml:mrow> <mml:msub> <mml:mtext>Hf</mml:mtext> <mml:mrow> <mml:mn>0.5</mml:mn> </mml:mrow> </mml:msub> <mml:msub> <mml:mtext>Zr</mml:mtext> <mml:mrow> <mml:mn>0.5</mml:mn> </mml:mrow> </mml:msub> <mml:msub> <mml:mtext>O</mml:mtext> <mml:mn>2</mml:mn> </mml:msub> </mml:mrow> </mml:math> (HZO), ensures a reduction in operating voltage and enhances HZO scaling while being compatible with CMOS circuits. The IL also enriches ferroelectricity and retention properties. When integrated into crossbar arrays, FeCaps and FeFETs demonstrate their effectiveness as IMC components, eliminating sneak paths and enabling selector-less operation, leading to notable improvements in energy efficiency and area utilization. However, it is worth noting that limited capacitance ratios in FeCaps introduced errors in multiply-and-accumulate (MAC) computations. The proposed co-design approach helps in mitigating these errors and achieves high accuracy in classifying the CIFAR-10 dataset, elevating it from a baseline of 10% to 81.7%. FeFETs in crossbars, with a higher on-off ratio, outperform FeCaps, and our proposed charge-based sensing scheme achieved at least an order of magnitude reduction in power consumption, compared to prevalent current-based methods. 

Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads.

Unlike the conventional way to use drain current as the read-out mechanism, ferroelectric field effect transistor (FeFET) can be read-out in a capacitive manner, namely non-volatile capacitor (nvCAP) mode. This small-signal nvCAP mode is different from large-signal P-V read-out in the ferroelectric random-access memory (FeRAM) configuration. The reliability aspects such as endurance, retention, and multi-level cell (MLC) are evaluated for the first time in this study. The tunable capacitance CGS-CGD of FeFET devices in 28nm foundry platform was programmed to ON and OFF states. Impact of defect generation and charge-trapping during the ferroelectric switching on the endurance and retention behavior of nvCAP is investigated. We find that the device sustains up to 107program-erase cycles until the Con/Coff ratio becomes ~1, and a C-V sweep performed on the fatigued device help ‘recover’ the device performance. By repeatedly performing recovery-endurance operation, we demonstrate a recovered endurance of 108 cycles.

Reliability Assesement of Ferroelectric nvCAP for Small-Signal Capacitive Read-Out

Analog computing-in-memory (CIM) using emerging resistive nonvolatile memory (NVM) technologies faces challenges, such as static power consumption, current flow-induced IR drop, and the need for multiple power-hungry ADCs. In this letter, we present ferroelectric capacitive array (FCA)-based energy/area-efficient CIM macro used for charge-domain multiply-and-accumulate operations, which addresses the challenges of resistive NVM CIMs. The proposed CIM macro involves encoding ternary input activations and weights into voltages, and enabling parasitic insensitive charge readout. A power-of-two nonlinear SAR ADC is introduced, designed for energy-efficiency and hardware-friendliness. This ADC employs adaptive conversion skipping based on input voltage, resulting in fine precision for concentrated input levels and coarse conversion for sparse input levels. The proposed FCA-based CIM macro in 180-nm CMOS demonstrates $16\times 8$ analog MAC operation with an energy efficiency of 1.75 TOPS/W and classification accuracy of 90.2% is obtained for the CIFAR-10 dataset.

A Dynamic Power-Only Compute-in-Memory Macro With Power-of-Two Nonlinear SAR ADC for Nonvolatile Ferroelectric Capacitive Crossbar Array

Using “capacitive” crossbar arrays for compute-in-memory (CIM) offers higher energy efficiency compared to “resistive” crossbar arrays. The non-volatile capacitive (nvCap) synapse has been recently reported in MFM and MFS stacks with asymmetric electrode interfaces. In this work, a foundry FeFET is leveraged as the capacitive synapse for the first time, where the tunable gate-to-drain and gate-to-source capacitances ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{{\text {gd}}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{{\text {gs}}}$ </tex-math></inline-formula> ) are exploited as the capacitive memory states. High capacitance on/off ratio (~25) is obtained by relatively low program/erase voltages (±3.5V). Furthermore, it is demonstrated by TCAD simulation that the physical origins of on-state and off-state capacitance are dominated by the inversion capacitance and the overlap capacitance, respectively. Based on these results, design guidelines are presented to further increase the on/off ratio. 

Tunable Non-volatile Gate-to-Source/Drain Capacitance of FeFET for Capacitive Synapse

To support vertical power delivery network (PDN) in heterogeneous 3-dimensional (H3D) integrated circuits with multi-tier stacking, we demonstrated high-voltage back-end-of- line (BEOL) compatible devices: tungsten-doped indium oxide (IWO) power transistors and high-breakdown voltage (VBD) superlattice MIM capacitors. The IWO power transistors have a VBD >12 V and a cutoff frequency of 1.5 GHz. Monolithic cointegration of enhancement(E)- and depletion(D)-mode transistors are demonstrated for high-side and low-side switches, respectively, to implement a switched-capacitor (SC) based DC- DC voltage converter. We further demonstrated on-chip superlattice capacitors for high VBD of ~11.2 V. Using calibrated measurement data from fabricated devices, a BEOL compatible DC-DC converter was designed to demonstrate efficient voltage conversion in a multi-tier H3D transformer accelerator with multiple domains: logic (0.75 V), eDRAM (1.5 V), and ferroelectric transistor (FeFET) non-volatile memory (3 V).

BEOL Compatible Oxide Power Transistors for On- Chip Voltage Conversion in Heterogenous 3D (H3D) Integrated Circuits

Low-frequency noise (LFN) characterization of ferroelectric field-effect transistor (FeFET) is performed. Two types of FeFET are compared, one with oxide-channel (W-doped, i.e, IWO) compatible back-end-of-line (BEOL) process, and the other with silicon-channel using front-end-of-line (FEOL) process. The LFN measurements are performed for ON and OFF memory state of the devices to study the effect of polarization on the noise performance. Furthermore, the normalized noise power spectral density (NNPSD) value is extracted, and the IWO FeFET shows lower value than the Si FeFET with a similar gate length. However, IWO FeFET has shown a higher NNPSD than IWO MOSFET. The LFN experimental data is an indicator of the interfacial trap density. We conclude that the BEOL process eliminates the interfacial layer and reduces the trap density, while the ferroelectric gate stack induces more carrier fluctuation than the dielectric gate stack due to the polarization effect.

Low-Frequency Noise Characteristics of Ferroelectric Field-Effect Transistors

Impact of the Endurance Measurement Methodology on Ferroelectric Field Effect Transistor Under the Capacitive Nondestructive Read

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Omkar Phadke

Author Tools

Chat about Author