Analog signal processing is fast and can address real world problems. The applications of battery powered analog and mixed mode electronic devices require designing analog circuits to operate at low voltage levels. In this paper, some of the issues facing analog designers in implementing low voltage circuits are discussed, and possible low voltage design techniques are examined. The authors describe briefly almost all low voltage design techniques suitable for analog circuit structures along with their merits and demerits.

Low voltage analog circuit design techniques

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

A pH sensor fabricated on a single chip by an unmodified, commercial 0.6-/spl mu/m CMOS process is presented. The sensor comprises a circuit for making differential measurements between an ion-sensitive field-effect transistor (ISFET) and a reference FET (REFET). The ISFET has a floating-gate structure and uses the silicon nitride passivation layer as a pH-sensitive insulator. As fabricated, it has a large threshold voltage that is postulated to be caused by a trapped charge on the floating gate. Ultraviolet radiation and bulk-substrate biasing is used to permanently modify the threshold voltage so that the ISFET can be used in a battery-operated circuit. A novel post-processing method using a single layer of photoresist is used to define the sensing areas and to provide robust encapsulation for the chip. The complete circuit, operating from a single 3-V supply, provides an output voltage proportional to pH and can be powered down when not required.

/pdf/design-of-a-single-chip-ph-sensor-using-a-conventional-0-6-2ajeq77tfh.pdf

Design of a single-chip pH sensor using a conventional 0.6-/spl mu/m CMOS process

Fingerprint-based wireless indoor positioning approaches are widely used for location-based services because wireless signals, such as Wi-Fi and Bluetooth, are currently pervasive in indoor spaces. The working principle of fingerprinting technology is to collect the fingerprints from an indoor environment, such as a room or a building, in advance, create a fingerprint map, and use this map to estimate the user’s current location. The fingerprinting technology is associated with a high level of accuracy and reliability. However, the fingerprint map must be entirely re-created, not only when the Wi-Fi access points are added, modified, or removed, but also when the interior features, such as walls or even furniture, are changed, owing to the nature of the wireless signals. Many researchers have realized the problems in the fingerprinting technology and are conducting studies to address them. In this paper, we review the indoor positioning technologies that do not require the construction of offline fingerprint maps. We categorize them into simultaneous localization and mapping; inter/extrapolation; and crowdsourcing-based technologies, and describe their algorithms and characteristics, including advantages and disadvantages. We compare them in terms of our own parameters: accuracy, calculation time, versatility, robustness, security, and participation. Finally, we present the future research direction of the indoor positioning techniques. We believe that this paper provides valuable information on recent indoor localization technologies without offline fingerprinting map construction.

/pdf/indoor-positioning-technologies-without-offline-1jzo5irih4.pdf

Indoor Positioning Technologies Without Offline Fingerprinting Map: A Survey

This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple- V th circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2013.0023

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

A programming technique for controlling the floating gates (FGs) in ultra-low-voltage (ULV) floating-gate circuits is presented. Simple ULV PG current-scaling and level-shifting circuits are discussed. The current scaling and level shifting are accomplished using only minimum sized transistors and floating capacitors. Floating-gate current multiplier and divider circuits are described. Measured results are provided,.

Programming floating-gate circuits with UV-activated conductances

Ultra-low-voltage (ULV) floating-gate differential amplifiers are presented. In this paper, we present several different approaches to CMOS ULV amplifier design. Sinh-shaped and tanh-shaped transconductance amplifiers are described. Measured results are provided.

/pdf/ultra-low-voltage-floating-gate-transconductance-amplifiers-gm6hun29g0.pdf

Ultra-low-voltage floating-gate transconductance amplifiers

In this paper, two different types of Vivaldi antenna are designed and tested suitable for electromagnetic beamforming. The first is an antipodal Vivaldi antenna, while the other is a tapered slot Vivaldi antenna. They are both ultra wideband antennas for the 1GHz to 5GHz frequency band. They have low impulse distortion and the voltage standing wave ratio (VSWR) less than 2 throughout the entire bandwidth. The antennas are used for impulse radio beamforming.

UWB Vivaldi antenna for impulse radio beamforming

We present a low-voltage/low power second order filter. The filter consists of 6 pseudo floating-gate transistors operated in weak inversion. The filter is suitable for any kind of application requiring low frequency ranges, such as biomedical products. An electronic cochlea consisting of replicas of the filter is presented. The filter operates at a supply voltage below 1 V, consumes power down to 5 nW, and has a harmonic distortion suppression of -60 dB.

A low voltage second order biquad using pseudo floating-gate transistors

A low-power impulse radio (IR) ultra wideband (UWB) pulse generator (PG) is presented. It uses digital gate-delay for timing achieving good power efficiency and acceptable spectral filling. The circuit is scalable in both bandwidth and center frequency. Both energy consumption and chip area are reduced compared to most conventional higher order Gaussian PGs. The PG is realized in a TSMC 90 nm CMOS process. Measurements show the energy consumption from a 1.2 V to be 5.2 pJ/pulse for a 200 MHz pulse repetition frequency (PRF). The core area is 0.0015 mm2 (38 µm×40 µm). Lastly, a dynamic pre-charge (DPC) scheme is proposed to eliminate the standby current and make the PG favourable for low-data-rate applications.

A 5.2 pJ/pulse impulse radio pulse generator in 90 nm CMOS

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