Monolithic integrated millimeter-wave circuits based on silicon and SiGe are emerging as an attractive option in the field of millimeter-wave communications and millimeter-wave sensors. The combination of active devices with passive planar structures, including also antenna elements, allows single-chip realizations of complete millimeter-wave front-ends. This paper reviews the state-of-the-art silicon- and SiGe-based monolithic integrated millimeter-wave circuits. The technological background as well as active and nonlinear devices and passive circuit structures suitable for silicon- and SiGe-based monolithic integrated millimeter-wave circuits are discussed. Examples of such integrated circuits and first systems applications are also presented.

Si and SiGe millimeter-wave integrated circuits

A novel cooling device fully built in silicon technology is presented. The new concept developed in this work consists of micromachining the bottom side of the circuit wafer in order to embed heat sinking microchannels directly into the silicon material. These microchannels are then sealed, by a direct wafer bonding procedure, with another silicon wafer where microchannels and inlet-outlet nozzles are micromachined too. A cooling fluid (water) is then forced through the array of channel to convey heat outside the chip. Such a configuration presents advantages to provide a significant reduction of the cooler overall dimensions, to reduce the number of the involved materials and to be compatible with integrated circuit fabrication procedures, In this study analytical tools were used in order to get a global evaluation of all the thermal resistances characteristic of such devices. Using these adequate analytic models with appropriate approximations, a global optimization procedure was then applied and led to the definition of he optimum dimensions of the silicon micro heat sink. The realization procedure was then carried out in a clean room environment. First experimental characterization results obtained from the earlier prototypes demonstrated that the thermal properties of this silicon-based cooling device are satisfactory and can be reasonably compared to those of commercially available copper micro heat sinking components.

Analytic modeling, optimization, and realization of cooling devices in silicon technology

A method is described for fabricating a module having a chip attached to a carrier substrate, wherein a guide substrate transparent to ablation radiation is used. A removable layer is provided on a surface of the guide substrate. A first alignment guide is formed on the removable layer, and a second alignment guide is formed on a front surface of the chip. The chip is aligned to the guide substrate by contacting the second alignment guide to the first alignment guide; the chip is then attached to the guide substrate. The carrier substrate is attached to the chip at the back surface of the chip. The interface between the removable layer and the guide substrate is then ablated using radiation (typically laser radiation) transmitted through the guide substrate, thereby detaching the guide substrate. Thin films with metal interconnections may then be provided on the front surface of the chip.

Process for precision alignment of chips for mounting on a substrate

A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.

Process for making fine pitch connections between devices and structure made by the process

Chronically implantable, wireless neural interfaces require biocompatible, long term stable, and high density integration of all functional sub-components. For this, the integration and interconnection concept of the wireless neural interface was proposed and interconnection materials and methods were investigated and characterized. The module consists of an electronics IC assembled to an electrode array. Thin film flex coils are glued onto the back side of the IC. The IC was interconnected by AuSn reflow flip chip bonding on the backside of the Utah electrode array (UEA) and off-chip electric components were SnCu0.7 soldered on the integrated IC/UEA module to guarantee a reliable connectivity.

Biocompatible hybrid flip chip microsystem integration for next generation wireless neural interfaces

MCM-D with Embedded Active and Passive Components

Thin film multilayer substrate technology with dielectric polymer layers and sputtered/electroplated wiring provide the highest line density per layer and therefore they are of special interest for MCM applications. A planar integration technology of bare dice embedded in ceramic substrates is used. The components are inserted into premanufactured windows of ceramic substrates and fixed in their position by epoxy. A thin film multilayer is realized in a planar fashion on top of the embedded system. The metallization is based on a Ti:W/ Cu tie layer, which is subsequently electroplated with Cu. Polyimid Pyralin 2722 (Du Pont) and Cyclotene 4026-46 (Dow Chemical) are used as interlevel dielectric. The paper addresses the transmission lines characteristics (MS and CPW) for the chip substrate interconnection. Furthermore, the effect of the meshed ground plane on the line parameter impedance is discussed. The dielectric polymer layers are characterized by the effective permittivity (e r ) and the loss factor (tan δ).

System integration for high frequency applications

The multichip module described in this paper is a prototype for a pixel detector system for the planned Large Hadron Collider L HC at CERN, Geneva. The research project is within the ATLAS experiment. It addresses the study of proton-proton interactions. A module consists of a sensor tile with an active area of 16.4mm x 60.4mm, 16 read-out chips, each serving 24 x 160 pixel unit ce lls, a module controller chip, an optical transceiver, a local signal interconnection, and power distribution busses. Two module con cepts were designed for this detector; MCM-D and MCM-L. In this paper, the MCM-D type will be discussed. The extremely high wiring density, necessary to interconnect the read-out chips, was achieved using a thin film Copper/Photo-BCB process above the pixel array. The bumping of the read out chips was achieved using electroplating PbSn. All dice are then attached by Flip Chip asse mbly to the sensor diodes and the local busses. The focus of this paper is the detailed description of the technologies (thin film BCB/Cu and PbSn bumping) for the fabrication of this advanced MCM-D using high-density Flip Chip assembly.

Fabrication of a high-density MCM-D for a pixel detector system using a BCB/Cu technology

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MCM-D with Embedded Active and Passive Components

System integration for high frequency applications

Fabrication of a high-density MCM-D for a pixel detector system using a BCB/Cu technology