This paper describes a low-power 1.2 V 8-bit 1Gs/s two-channel pipeline ADC. The novelty of the designed ADC lies in: ameliorating the two-channel pipeline structure that consists of 1.5-bit multiplying DAC (MDAC). In order to reduce the power consumption and improve the sampling speed, the dual-channel pipeline Time Division Multiplexing operation amplifier and double or single channel flash ADC are used; in the front-end Sample-and-Hold circuits, switch-linearization control circuits(SLC) driven by a single clock signal is applied to solve the problem of time-skew and time mismatch between two channels. The pipeline ADC is designed with 90 nm CMOS process. From the simulation results of the designed ADC, we can draw that the SFDR is 42.3 dB; the SNR is 32.7 dB under the usual temperature. The ADC achieves 21 mW power-dissipation, 8 resolution and 1.01 GS/s sampling speed. So the design meets high speed, high precision and low power dissipation at the same time.

Design of High-Speed and Low-Power Two-Channel Pipeline ADC

In order to obtain high-speed and large-drive-current during operation, this paper proposed two structure-advanced BiCMOS analog switches. On the key parts of the circuit, a few Bipolar Junction Transistors (BJTs) were used while for the main parts, the Complementary Metal Oxide Semiconductor (CMOS) devices were configured. The component parameters were optimized and the measures for accelerating the operation and raising the drive-current were taken. The performance of the proposed two analog switches was tested through simulation and experiments of hardware circuits. The results indicated that the Delay-Power Product (DP) of the BiCMOS operating in the voltage range of 2.5V~3.5V is reduced by an average of 26.1pJ and the driving current is more than 1.38mA as compared with those of the conventional CMOS analog switches. These advantages show the great potential of the proposed two BiCMOS analog switches in the digital communication systems which require low-voltage, high-speed and large-drive-current.

Two High-Speed and Large-Drive-Current BiCMOS Analog Switches

A high-precision amplifier design in a stander 0.35μm CMOS process was proposed. This design obtains a high-performance by proper application of dynamic element matching to a second generation current conveyor (CCII). In comparison with the traditional CMOS circuits, the proposed approach can not only increase the output swing and decrease output resistance but also compensate the effect of the input offset and 1/f noise voltage. The simulation results show that the gain error is reduced 38~50 times than the traditional amplifier, and the precision is significantly improved. So the proposed circuit is suitable for the design of special amplifiers used in various detections and signal mediation.

Design of CMOS Amplifier Using New CCII Topologies

Droplet drift is always an accompaniment of pesticide spraying and can cause serious consequences. In this paper, we used a computational fluid dynamics software package (FLUENT) to analyze flow fields of spraying with air jet under different conditions in the tunnel model, and compared the effect of air jet on spray deposition and drift. Results of this study indicate that air jet can act directly on the spray droplets and affect their distribution and movement. Larger jet velocity has better performance on the drift reduction and droplet deposition. Droplets in the flow fields with larger jet velocity can get more kinetic energy and arrive at the root of crops easilier. When droplets are released straight down, larger velocity of droplets can be given and better performance can be achieved either in terms of drift reduction or droplet deposition.

CFD Simulation of Spraying with Air Jet

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Papers

Design of High-Speed and Low-Power Two-Channel Pipeline ADC

Two High-Speed and Large-Drive-Current BiCMOS Analog Switches

Design of CMOS Amplifier Using New CCII Topologies

CFD Simulation of Spraying with Air Jet