This paper presents an efficient VLSI architecture of the 2-D wavelet transform for the adaptive directional lifting (ADL) scheme in image coding. To avoid accumulating errors from irrational wavelet transform coefficients, algebraic integers with appropriate input scaling parameters are used. A two-parallel architecture with zigzag processing of the image stream is used to increase the throughput. In a 45-nm CMOS technology, the synthesis results indicate that the proposed architectures for the Daub-4 and 5/3 wavelets can operate at a clock frequency of about 250 MHz with an estimated throughput of 4 Gb/s.

Adaptive Directional Lifting Wavelet Transform VLSI Architecture

Because of high data dependency between ADL (adaptive directional lifting) steps, such as interpolation, directional prediction and update, the existing CUDA (Compute Unified Device Architecture) configuration method for traditional rectilinear transform is difficult to be used for ADL-based transform. This paper proposed a new configuration method so-called Slice for implementation of the ADL-based transforms on GPUs (Graphics Processing Units). Compared with the existing configuration for the conventional rectilinear lifting algorithm, the proposed method makes each step being handled by a different kernel both for horizontal and vertical passes to avoid unnecessary waiting time between threads. Meanwhile the interpolation and decomposition are executed in an interleaving manner on the pixel level. Moreover, the coalesced memory accesses are exploited to the greatest extent by reading and writing a slice of image data from or back to global memory. The results show that the Slice method overcomes the limitation of high data dependency between ADL steps, and achieves more than 10 times speedup compared to the optimized CPU implementation.

Accelerating adaptive directional lifting based wavelet decomposition on GPU using CUDA

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Accelerating adaptive directional lifting based wavelet decomposition on GPU using CUDA