How to control solid state dewetting: A short review

The concept of direct band gap group IV materials offers a paradigm change for Si-photonics concerning the monolithic implementation of light emitters: The idea is to integrate fully compatible group IV materials with equally favorable optical properties as the chemically incompatible group III-V-based systems The concept involves either mechanically applied strain on Ge or alloying of Ge with Sn and permits to drastically improve the insufficient radiative efficiency of Ge The favorable optical properties result from a modified band structure transformed from an indirect to a direct one The first demonstration of such a direct band gap laser, accomplished in GeSn, exemplifies the capability of this new concept These systems may permit a qualitative as well as a quantitative expansion of Si-photonics into traditional but also new areas of applications, provided they can be operated energy efficiently, under ambient conditions and integrated with current Si technologies This review aims to discuss the challenges along this path in terms of fabrication, characterization and fundamental understanding, and will elaborate on evoking opportunities of this new class of group IV-based laser materials

/pdf/group-iv-direct-band-gap-photonics-methods-challenges-and-51g3knwf2r.pdf

Group IV direct band gap photonics: Methods, Challenges and Opportunities

Germanium based photonic components toward a full silicon/germanium photonic platform

Challenges and opportunities in advanced Ge pMOSFETs

Device concepts are applied to strained layers ranging from pure Si to pure Ge to achieve higher carrier mobilities. Strain is generated by growth on Si 1―x Ge x buffer layers with an appropriate Ge content. Processing of these heterostructures requires selective removal of individual layers. Different approaches to the etch Si, Si 1―x Ge x , and Ge layers have been evaluated in terms of the etch rate, selectivity, and isotropy. All investigated etching methods used highly selective chemical etching solutions composed of HF, hydrogen peroxide, and acetic acid (HF:H 2 O 2 :CH 3 COOH). The effect of the different HF content on the etch rate of pure Si, pure Ge, and Si 1―x Ge x alloys with Ge mole fractions between 20 and 75% is presented. In general, the etch rate increases significantly with the increase in Ge content. As an example, the etch rate increases by a factor of more than 100 when the Ge content increases from 20 up to 75 atom %.

Wet Chemical Etching of Si, Si1-xGex, and Ge in HF:H2O2:CH3COOH

SOITEC, Parc Technologique des Fontaines, F38190, Bernin, France The recent progress in the fabrication of GeOI substrates and devices is reviewed. Improvements have been made in threading dislocation density, Ge-buried oxide interface passivation, device performance. The potential of various co-integration schemes (lateral and vertical) has been illustrated as alternatives to the fabrication of n-type germanium channel devices. GeOI is also shown to be a versatile platform for the monolithic integration of Si and III-V devices and tunneling field effect transistors.

Challenges and Progress in Germanium-on-Insulator Materials and Device Development towards ULSI Integration

Smart Cut® Technology has recently been moved forward to a performance that seemed impossible until just recently. FDSOI requirements demand a method to transfer an ultra-thin crystalline layer with near perfect uniformity. Silicon thickness variation across all UTBOX wafers has reached +/- 5 A all points all wafers, while at the same time roughness has been improved to reach 0.8 A 30x30 µm2 RMS. BOX is available over a wide range of thicknesses from 10 to 50nm, ready to satisfy all possible applications. Such development efforts have now passed process technology qualification [1] and provided a proven path for further node scaling [2]. This paper reports the latest achievements in state of the art thickness and roughness control, which is enabling very low variability for fully depleted devices today.

Atomic Scale Thickness Control of SOI Wafers for Fully Depleted Applications

Since 90nm technology Germanium (Ge) element has become increasingly popular in the CMOS processing for enhancing transistor performance, especially enhancing hole mobility for P-type transistors. The main driver has been the embedded SiGe in the source/drain region and its extraordinary boost on PFET drive current [1]. More recently Ge has enabled band engineering with respect to Silicon for Vt tuning [2,3] in addition to channel engineering for mobility enhancement. Looking into the future the need for SiGe alloys or pure Ge is increasing, as it is contemplated as a seed for IIIV material growth [4], or even the replacement of Si by Ge in the channel to take advantage of the high electron and hole mobilities [5]. Today the manufacturing reality shows us that all Ge needs can be fulfilled by epitaxy during the processing of the devices [6]. In this paper we will introduce the Dual Channel substrate having a strained SiGe layer grown on top of a SOI substrate. Starting with this wafer and thru condensation process one can produce a uniform SiGe layer suitable for Fully Depleted applications.

SiGe and Ge on Insulator Wafers

Invited) Manufacturing of Ultra Thin SOI

http://ma.ecsdl.org/content/MA2012-02/32/2634.full.pdf

Manufacturing of Ultra Thin SOI

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