Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems. This paper proposes new ternary combinational digital circuits that reduce energy consumption in low-power nano-scale embedded systems and Internet of Thing (IoT) devices to save their battery consumption. The 32 nm CNTFET-based ternary half adder (THA) and multiplier (TMUL) circuits use novel ternary unary operator circuits and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. Extensive simulations (over 160) of the proposed designs in terms of PVT (Process, Voltage, Temperature) variations, noise effect, and scalability studies, along with several benchmark designs using HSPICE simulator, prove the significance of the proposed circuits to decrease the power-delay product (PDP), improve the robustness to process variations, and the noise tolerance. The obtained results show the superiority of the designs in a reduction between 32% and 74% in transistors count and between 18% and 99% in PDP compared to the most recent works.

/pdf/novel-ternary-adder-and-multiplier-designs-without-using-31suaqk2x0.pdf

Novel Ternary Adder and Multiplier Designs Without Using Decoders or Encoders

Efficient ternary comparator on CMOS technology

Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier

Multi-level electronic systems offer speed and area simplicity, reducing the complexity of implementation and power dissipation. In this paper, a Hybrid ternary Full Adder (FA) is proposed using Conventional Complementary Metal Oxide Semiconductor (CCMOS), Double Pass-transistor Logic (DPL), and Pass Transistors (PT). The proposed FA is extended up to 64-bits to test scalability. To validate the proposed full adder and calculate its performance analysis, the Cadence Virtuoso toolset is used at technology 130nm with supply voltage 0.9V. An extra transistor is added to overcome the sneak path problem that was detected during the simulation. The ternary values 0, 1, and 2 are represented with 0V, 0.45V and 0.9V respectively. According to the simulation results, the proposed work shows a superior performance, which could be considered a promising alternative for low power applications.

Low Power Scalable Ternary Hybrid Full Adder Realization

This work proposes novel strategy to design 2-input ternary (base-3) logic circuits using double pass-transistor logic (DPL). The concept has been explored with respect to 2-input TXOR gate. The circuit diagram of proposed DPL-based TXOR, TAND and TOR logic gate is presented. The proposed T-Cells are designed and optimised using BSIM3 device model with 1.8 V supply rail and at 25°C temperature on TSMC 0.18 µm CMOS technology. The transient response from T-Spice simulatio is validated and the speed-power performance is recorded. Next, the 2:9 ternary decoder based on proposed idea has been explained. The decoder circuit is also designed with 1.8 V supply rail at 25°C temperature on TSMC 0.18 µm CMOS technology. The trit value '0', '1' and '2' are represented with 0 V, 0.9 V and 1.8 V respectively. As per simulation result the proposed 2:9 ternary decoder dissipates 383.57 µW average power and takes 64.87 ps to generate final output.

Systematic design strategy for DPL-based ternary logic circuit

Present paper introduces a novel strategy to design Double Pass-transistor Logic (DPL)based Ternary (base-3)logic circuit in favour of wave-pipelined applications. Ternary can be a feasible candidate to replace conventional binary (base-2)number system due to faster computation, reduced interconnect complexity, reduced fan-in/fan-out, less storage requirement and so on. Careful design with proper coarse and fine tuning of wave-pipelined circuit can improve the overall performance and reliability of digital SOC. DPL is a favourable candidate for wave-pipelining and is employed in this work. Ternary digit (“trit”)value “0”, “1” and “2” are coded with 0 V, 0.9 V and 1.8 V respectively. In order to validate proposed strategy the 2-input TXOR, TAND and TOR circuits are designed and the simulation results are verified. Speed-power performance of designed circuit is recorded. All the simulations are carried out on TSMC $0.18\mu\mathrm{m}$ CMOS technology with 1.8 V supply rail and at 25°C temperature using Tanner EDA.V13.

Novel Approach to Design DPL-based Ternary Logic Circuits

Subtraction is a fundamental numerical operation necessary for most arithmetic and logic computation. Ternary is a promising alternative in order to suppress demerits associated with present high-density binary (Radix-2) based digital Integrated Circuits. The present paper introduces a new strategy to design ternary (Radix-3) 1-trit half-subtractor based on Double Pass-transistor Logic (DPL) for Time-equalized/wave-pipelined digital applications. Wave-pipelining improves circuit performance without intermediate latches/flip-flops and hence can suppress difficulties of register pipelining. The proposed DPL-based ternary subtractor finds application to design low-power high-speed wave-pipelined ternary digital processing system. The complete circuit is designed and optimized with normal process E-MOS devices using BSIM3 model parameters. Ternary digit ‘0’, ‘1’ and ‘2’ are represented by 0 V, 0.9 V and 1.8 V, respectively. Transient response with T-Spice simulation validates the proposed idea. The extracted speed–power performance is recorded. All the simulations are performed on TSMC 0.18 µm CMOS technology with 1.8 V supply rail and at 25 °C temperature using Tanner EDA v13.

DPL-Based Novel 1-Trit Ternary Half-Subtractor

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Papers

Efficient ternary comparator on CMOS technology

Systematic design strategy for DPL-based ternary logic circuit

Novel Approach to Design DPL-based Ternary Logic Circuits

DPL-Based Novel 1-Trit Ternary Half-Subtractor