Recent advances in experimental techniques (on-the- fly and ultrafast techniques) allow measurement of threshold voltage degradation due to negative-bias temperature instability (NBTI) over many decades in timescale Such measurements over wider temperature range (-25degC to 145degC), film thicknesses (12-22 nm of effective oxide thickness), and processing conditions (variation of nitrogen within gate dielectric) provide an excellent framework for a theoretical analysis of NBTI degradation In this paper, we analyze these experiments to refine the existing theory of NBTI to 1) explore the mechanics of time transients of NBTI over many orders of magnitude in time; 2) establish field dependence of interface trap generation to resolve questions regarding the appropriateness of power law versus exponential projection of lifetimes; 3) ascertain the relative contributions to NBTI from interface traps versus hole trapping as a function of processing conditions; and 4) briefly discuss relaxation dynamics for fast-transient NBTI recovery that involves interface traps and trapped holes

/pdf/recent-issues-in-negative-bias-temperature-instability-516v1ys8p8.pdf

Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation

The microelectronics industry owes its considerable success largely to the existence of the thermal oxide of silicon. However, recently there is concern that the reliability of ultra-thin dielectrics will limit further scaling to slightly thinner than 2 mm. This paper will review the physics and statistics of dielectric wearout and breakdown in ultrathin SiO/sub 2/-based gate dielectrics. Electrons or holes tunneling through the gate oxide generate defects until a critical density is reached and the oxide breaks down. The critical defect density is explained by the formation of a percolation path of defects across the oxide. Only 1 year) stress experiments are now being used to measure the wearout and breakdown of ultrathin (<2 nm) dielectric films as close as possible to operating conditions. These measurements have revealed the details of the voltage dependence of the defect generation rate and critical defect density, allowing better modeling of the voltage dependence of the time-to-breakdown, Such measurements are used to guide the technology development prior to the manufacturing stage. We then discuss the nature of the electrical conduction through a breakdown spot and the effect of the oxide breakdown on device and circuit performance. In some cases, an oxide breakdown does not lead to immediate circuit failure, so more research is needed in order to develop a quantitative methodology for predicting the reliability of circuits.

/pdf/physical-and-predictive-models-of-ultrathin-oxide-44bw6q1dcp.pdf

Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits

The present understanding of wear-out and breakdown in ultrathin (t/sub ox/ < 5.0 nm) SiO/sub 2/ gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed.

Ultrathin gate oxide reliability: physical models, statistics, and characterization

This paper presents a comprehensive, numerical model for the remote Coulomb scattering (RCS) in ultrathin gate oxide MOSFETs due to ionized impurities in the polysilicon. Using a nonlocal screening approach, the model accounts for the static screening of the scattering centers produced both by electrons in the channel and in the polysilicon. Electron mobility is then calculated using a relaxation time approximation that consistently accounts for intersubband transitions and multisubband transport. Our results indicate that neglecting the screening in the polysilicon and making use of the Quantum Limit (QL) approximation can lead to a severe underestimate of the RCS limited electron mobility, thus hampering the accuracy of the predictions reported in some previous papers on this topic. Using our model, we discuss the oxide thickness dependence of the electron mobility in ultrathin gate oxide MOSFETs and the possible benefits in terms of RCS limited mobility leveraged by the use of high K dielectrics.

Modeling of electron mobility degradation by remote Coulomb scattering in ultrathin oxide MOSFETs

Gate oxide reliability is an essential factor in qualifying CMOS technologies. An accurate and consistent methodology for determining ultrathin oxide reliability is therefore needed. In this paper, the crucial steps of this methodology are analysed. First it is demonstrated that soft and hard breakdown show an identical distribution and therefore extrapolation, from the test voltage to a voltage where the soft to hard breakdown prevalence ratio is different, is allowed. Secondly, the log-normal distribution is shown to be inadequate to describe the tBD-statistics; only the Weibull distribution can be used. Thirdly, based on stress-induced leakage current measurements, it is concluded that a ln(tBD)-Vg-dependence is well suited to extrapolate high voltage tBD-data to low voltage. It is demonstrated that in the 1 to 2 V range, the gate voltage shows no threshold value below which the oxide degradation is reduced or altered. A detailed analysis in the oxide thickness range 2 to 5 nm is presented showing that oxide reliability might become a major showstopper for the further downscaling of CMOS technology. Possible flaws in the reliability prediction methodology are discussed and guidelines for future research are indicated.

https://iopscience.iop.org/article/10.1088/0268-1242/15/5/302/pdf

Reliability: a possible showstopper for oxide thickness scaling?

In this paper we report on the self-consistent modeling and simulation of quantization effects and tunneling current in MOS devices. The simulation model features an original scheme for the self-consistent solution of Poisson and Schrodinger equations and it is used for the extraction of the oxide thickness, by fitting CV curves, and the calculation of the tunneling current. Simulations and experiments are compared for different device types and oxide thicknesses (1.5-6.5 nm) showing good agreement and pointing out the importance of quantum mechanical modeling and the presence of many tunneling mechanisms in ultra-thin oxide MOS devices.

http://ieeexplore.ieee.org/iel5/6469/17293/00799305.pdf

Self-consistent simulation of quantization effects and tunneling current in ultra-thin gate oxide MOS devices

We demonstrate that reliability projections can be improved significantly if oxide thickness uniformity is improved Our results include a Weibull slope of 138 for an extremely uniform 16 nm oxide, and also a steeper voltage scaling factor than has been used in the past Transistors with 50 nm gate-length and /spl sim/15 nm oxides exhibit soft breakdown, suggesting that it may be possible to relax current reliability specifications

Gate oxides in 50 nm devices: thickness uniformity improves projected reliability

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Self-consistent simulation of quantization effects and tunneling current in ultra-thin gate oxide MOS devices

Gate oxides in 50 nm devices: thickness uniformity improves projected reliability