A method for producing a semiconductor device includes the steps of: forming an impurity diffusion layer for controlling a threshold voltage by ion implantation; and conducting a high-temperature rapid heat treatment for recovering crystal defects generated by the ion implantation. More specifically, treatment conditions for the high-temperature rapid heat treatment are set in such a manner that interstitial atoms causing the crystal defects are diffused, and impurities in the impurity diffusion layer are not diffused. For example, the high-temperature rapid heat treatment is conducted in a temperature range of about 900 DEG C to about 1100 DEG C.

Method for manufacturing semiconductor device

This paper investigates anomalous diffusion behavior for ultra low energy implants in the extension or tip of PMOS devices. Transient enhanced diffusion (TED) is minimal at these low energies, since excess interstitials are very close to the surface. Instead, interface induced uphill diffusion is found, for the first time, to dominate during low temperature thermal cycles. The interface pile-up dynamics can be taken advantage of to produce shallower junctions and improve short channel effect control in PMOS devices. Attempts to minimize TED before spacer deposition by inclusion of extra RTA anneals are shown to be detrimental to forming boron ultra shallow junctions.

/pdf/interface-induced-uphill-diffusion-of-boron-an-effective-4rps4stmh9.pdf

Interface induced uphill diffusion of boron: an effective approach for ultrashallow junction

We have shown that ion-implanted boron (B) in an amorphous layer formed through Ge ion implantation becomes highly active during solid-phase epitaxy. The activated B concentration reaches about 10/sup 20/ cm/sup -3/ and is almost completely independent of the temperature. This active concentration corresponds to the solid solubility at 900/spl deg/C, hence the B becomes active at levels greater than the solid solubility below this temperature. This activated B was deactivated as a result of the subsequent thermal process in which the diffusion length reached about 10 nm. A low-resistance shallow junction can thus be realized in the low-temperature region provided we end the annealing before the onset of the rise in resistance.

High activity of B during solid-phase epitaxy in a pre-amorphized layer formed by Ge ion implantation and deactivation during a subsequent thermal process

This work shows a new methodology which automates the necessary links between technology computer aided design (TCAD) and the semiconductor manufacturing environment to a high extent Initially a short overview of a typical chain of processes during the fabrication of an integrated circuit is given Furthermore an overview on the relations to the respective simulator tools is given The interfaces between the fabrication process and simulation are identified and the detailed structure of the interfaces is outlined A comprehensive overview over the interactions in this integrated system is given as well Finally the strengths of such a structured and integrated approach are demonstrated with a case in a real semiconductor fabrication environment

TCAD as an integral part of the semiconductor manufacturing environment

The impact of the cathode geometry on conduction and switching properties of high voltage trench gate IGBTs is analysed using mixed mode two-dimensional device and circuit simulation tools. The most effective means to minimize conduction losses by injection enhancement at the cathode is the reduction of the width of the mesa containing n/sup +/ electron emitters and the MOS channel regions. As compared to planar IGBTs, the improvement is most pronounced at higher operating temperatures. If low short circuit current densities are of concern, optimized trench gate geometries also require wide trenches. Trading off conduction losses against turn-off losses, trench gate IGBTs generate approximately 30 to 40% less turn-off losses as planar IGBTs with identical on-state voltage.

On-state and short circuit behaviour of high voltage trench gate IGBTs in comparison with planar IGBTs

We propose to use a fixed damage factor combined with an effective dose to generate an initial interstitial silicon concentration profile at a given B ion implantation conditions and demonstrate that this methodology can readily explain transient enhanced diffusion (TED) in almost all relevant cases of practical VLSI processing. We also developed a B cluster reaction model which enables us to tune time evolution of active B profiles in a flexible way.

Damage calibration concept and novel B cluster reaction model for B transient enhanced diffusion over thermal process range from 600/spl deg/C (839 h) to 1100/spl deg/C (5 s) with various ion implantation doses and energies

The simulation of power semiconductor devices is faced with several problems that are not usually found in VLSI device modeling: the huge and often complicated structures, the interaction with external circuit environment, the effects of surface phenomena, etc The large variety of device structures and the lack of compact circuit models makes TCAD very important for the design and optimization of these devices >

TCAD in power device design and optimization

Analyzing experimental boron transient diffusion profiles in Si MOSFETs over a wide temperature range with the process simulator TESIM, we evaluated the related transient diffusion time t/sub E/, enhanced diffusivity D/sub enh/, and maximum transient diffusion concentration C/sub enh/. Our extracted values contradict previously reported values, but it is due to the fact that the former works neglected the ramp-up period. We show that considering the ramp-up period is indispensable for the analysis of transient diffusion. We also developed analytical models for t/sub E/, D/sub enh/, and C/sub enh/, and clarified their dependence on physical parameters implemented in TESIM.

Analytical models for transient diffusion and activation of ion-implanted boron during rapid thermal annealing considering ramp-up period

This paper will provide an example for improved technology understanding through a combination of simulation and measurements. Sample mispreparations and design errors could be detected very fast with process simulation, an extremly helpful tool to correlate physical and electrical measurements.

/pdf/improved-technology-understanding-through-using-process-w40dqxyuvg.pdf

Improved Technology Understanding through Using Process Simulation and Measurements

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Papers

Damage calibration concept and novel B cluster reaction model for B transient enhanced diffusion over thermal process range from 600/spl deg/C (839 h) to 1100/spl deg/C (5 s) with various ion implantation doses and energies

TCAD in power device design and optimization

Analytical models for transient diffusion and activation of ion-implanted boron during rapid thermal annealing considering ramp-up period

Improved Technology Understanding through Using Process Simulation and Measurements