This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

Strain engineering using lattice-mismatched S/D in transistors and their combination with other stressors and optimum surface/channel orientations is very attractive and important for the continued improvement of CMOS performance in addition to device scaling

https://iopscience.iop.org/article/10.1088/0268-1242/22/1/S42/pdf

Enhancing CMOS Transistor Performance Using Lattice-Mismatched Materials in Source/Drain Regions

This article is targeted as an introduction to the physics of strained Si and the current state of the art in uniaxial strained Si MOSFET. The first part of the article explains how strain alters the valence and conduction band of Si as well as scattering rates. This is followed by a review of state-of-the-art strained techniques being implemented in 90- and 65-nm process technologies. Finally, we conclude with a discussion of the future scalability of strained Si MOSFETs in the ballistic regime and nanoscale CMOS.

http://ieeexplore.ieee.org/iel5/101/32496/01517386.pdf

Mobility enhancement

A method for depositing a carbon doped epitaxial semiconductor layer (30) comprises maintaining a pressure of greater than about 700 torr in a process chamber (122) housing a patterned substrate (10) having exposed single crystal material (20). The method further comprises providing a flow of a silicon source gas to the process chamber (122). The silicon source gas comprises dichlorosilane. The method further comprises providing a flow of a carbon precursor (132) to the process chamber (122). The method further comprises selectively depositing the carbon doped epitaxial semiconductor layer (30) on the exposed single crystal material (20).

Epitaxial deposition of doped semiconductor materials

Strain greatly affects the electrical properties of silicon because strain changes the energy band structure of silicon. In MOSFET devices, the terminal voltages induce electrical fields, which themselves modulate the electronic band structure and interact with strain-induced changes. Applied electrical fields are used to experimentally study different state-of-the-art local and global strain techniques and reveal the different responses of n- and p-MOSFETs to the different strain techniques. It is shown that p-MOSFETs have more low-lateral-field linear drive-current enhancement and less high-lateral-field saturation drive-current enhancement at both low and high vertical fields. The situation is similar for n-MOSFETs at low vertical fields. However, at high vertical fields, n-MOSFET low-lateral-field linear drive-current enhancement is less than the high-lateral-field saturation drive-current enhancement. The origin for this behavior can be found in the different strain effects on the electronic band structure, which results in effective mass reduction and/or scattering suppression. These, in turn, contribute differently to linear and saturation drive-current enhancements in n- and p-MOSFETs.

Understanding Strain-Induced Drive-Current Enhancement in Strained-Silicon n-MOSFET and p-MOSFET

We report for the first time PMOS drive current enhancement with in-situ boron doped SiGe incorporation in recessed S/D regions for devices built on thin body SOI substrate. For P-channel PD-SOI devices with 450 A silicon on insulator and 38nm gate length, 35% linear drain current enhancement and 20% saturation drain current improvement have been achieved with this approach. Device integration and performance improvement are discussed below.

Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement

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Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement