Systolic arrays are hardware structures built for fast and efficient operation of regular algorithms that perform the same task with different data at different time instants. Systolic arrays replace a pipeline structure with an array of processing elements that can be programmed to perform a common operation. Regularity, reconfigurability and scalability are some of the features of systolic design. Systolic architectures offer the competence to uphold the high-throughput capacity requirement. Multi-dimensional image processing algorithms, video streaming, nonlinear optimization problems and decision based algorithms are a few of many algorithms that are computationally demanding and can be benefited by implementing systolic arrays. To satisfy a highly held comparison parameter of computational efficiency, there exists a bottleneck of memory hierarchy. It is undeniable that hardware and software have to go hand in hand to remove the bottleneck and achieve better performance. Any regular algorithm such as matrix multiplication can be implemented in systolic architecture through mapping hardware computations to a space time transformation using a dependence graph. Systolic design methodology maps an N-dimensional dependence graph to a lower-dimensional systolic architecture using a transformation. Mapping is a process of assigning each point in iteration space a scheduled processing element for the operation at discrete time. Mapping can be done heuristically with high cost in accuracy and design time. Evolutionary algorithms act as an alternative solution for efficient search for mapping solutions. The evolutionary algorithms belong to non-traditional techniques which mimic the biological behavior of organisms to obtain the solution. They duplicate the nature of species evolution, group of ants, swarm of birds, school of fishes, groups of frogs, etc. The decision of choosing an evolutionary algorithm for the mapping process is based on its swift learning capabilities and less computation time compared to traditional random, exhaustive search procedures. Evolutionary algorithms start with a population of possible solutions and, through biological operators such as crossover, mutation, evolution based on social behavior and personal experience, the algorithm moves to a better solution. Differential evolution, bacterial foraging optimization, bees algorithm, genetic algorithm, particle swarm optimization, memetic algorithm, ant colony optimization, and shuffled frog leaping algorithm are some of the evolutionary algorithms, and a few of the listed processes are discussed in this chapter. This discussion is an accolade for an architecture that has been developed for the main reason of improving the hardware utilization efficiency, cost effectiveness and performance of iterative algorithms. Grey tone difference matrix generation in texture analysis [1] is taken as an example to prove the efficiency of systolic arrays that are mapped with evolutionary algorithms. Parameters for comparing the efficiency of the algorithms are the number of iterations for which there has been no improvement in the cost function, mapping matrices, average value of the cost function and processing time in achieving the desired result.

Evolutionary Mapping Techniques for Systolic Computing System

A new class of fast Fourier transform (FFT) architecture, based on the use of distributed memories, is proposed for field-programmable gate arrays (FPGAs). Prominent features are high clock speeds, programmability, reduced look-up-table (LUT) and register usage, simplicity of design, and a capability to do both power-of-two and non-power-of-two FFTs. Higher clock speeds are a consequence of new algorithms and a more fine-grained structure compared to traditional pipelined FFTs, so clock speeds are typically >500 MHz in 65 nm FPGA technology. The programmability derives from the memory-based architecture, which is also scalable. Reduced LUT and register usage arises from a unique methodology to control word growth during computation that achieves high dynamic range, along with inherent systolic circuit characteristics: simple, regular, uniform arrays of processing elements, connected in nearest-neighbor fashion to minimize wiring lengths. The circuit goal was to maximize throughput and minimize the use of the FPGA LUT and register logic fabric. Comparison results from seven different designs, covering a spectrum of functionality (fixed-size, variable, floating-point and variable non-power-of-two FFTs), different FPGA vendors (Intel and Xilinx) and different FPGA types, showed increases in throughput per logic cell up to 181% with an average improvement of 94%.

https://www.mdpi.com/2079-9292/7/7/116/pdf/1

Distributed-Memory-Based FFT Architecture and FPGA Implementations

The authors present a technique for transforming DSP (digital signal processing) algorithms to a form suitable for multidimensional systolic array implementation. The aim of the transformation is to speed up computation without much increase in area requirement. The price to be paid is the small amount of additional circuitry (usually in the form of adders and interconnection wires) required for interrow or interplane communications. The application of the technique to some DSP algorithms is presented. The systolic networks produced are implemented using NORA CMOS logic structure and laid out using 3- mu m CMOS p-well technology. Areas and times for the resulting architectures are evaluated and discussed. >

The design and implementation of multidimensional systolic arrays for DSP applications

Portable multimedia systems require high performance, high efficiency, and the ability to exploit future gigascale VLSI technology. Limits of fixture on-chip interconnect, as projected in the National Technology Roadmap for Semiconductors (NTRS), increase communication costs and prevent the scaling of existing architectural approaches. New architectures must better exploit physical data locality to reduce the demand on global interconnects. This dissertation presents a system-level approach to localize computation and communication in an efficient computing platform. Research contributions include system models that capture interconnect-demand and describe architectures in gigascale technologies, and systolic synthesis procedures to map algorithms for area I/O arrays using planar streams. The system models average 60% more accurate in predictions of wire demand than existing stochastic models. A new area I/O systolic architecture is presented to exploit the physical locality of planar data streams by processing the data where it falls. New synthesis procedures for planar data streams presented in this thesis provide a three times increase in performance over previous techniques. Simulation results show that area I/O can provide additional average speedups of 16 times by exploiting additional data parallelism. This systolic array is approximately two orders of magnitude more area and power efficient than DSP and general-purpose microprocessors.

Real time image processing on parallel arrays for gigascale integration

This paper presents a new technique for mapping algorithms onto regular (systolic) arrays. The technique integrates the associativity and commutativity of computations into space-time transformations on the polytope model and involves three categories of transformations: ( 1) iso-planes - forming iso-planes of computations for algorithm representation in contrast to the conventional technique using the data dependence graph; ( 2) increase in dimensionality -mapping a low dimensional algorithm representation into a higher dimensional version with a higher degree of parallelism; and (3) pipestructures - generating and choosing a particular partial order of computations on iso-planes for moving data around the regular array. Three operations for generating pipestructures are introduced: permutation, rotation and reversal. The method presented here increases the available degree of parallelism and thus improves the time complexity of systolic computations. Examples for developing 2-D arrays for 1-D c...

Efficient mapping reductions using iso-planes on the polytope model

Systematic algorithm mapping for multidimensional systolic arrays

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Systematic algorithm mapping for multidimensional systolic arrays