This paper proposes a self-adaption Kalman observer (SAKO) used in a permanent-magnet synchronous motor (PMSM) servo system. The proposed SAKO can make up measurement noise of the absolute encoder with limited resolution ratio and avoid differentiating process and filter delay of the traditional speed measuring methods. To be different from the traditional Kalman observer, the proposed observer updates the gain matrix by calculating the measurement noise at the current time. The variable gain matrix is used to estimate and correct the observed position, speed, and load torque to solve the problem that the motor speed calculated by the traditional methods is prone to large speed error and time delay when PMSM runs at low speeds. The state variables observed by the proposed observer are used as the speed feedback signals and compensation signal of the load torque disturbance in PMSM servo system. The simulations and experiments prove that the SAKO can observe speed and load torque precisely and timely and that the feedforward and feedback control system of PMSM can improve the speed tracking ability.

Speed Measurement Error Suppression for PMSM Control System Using Self-Adaption Kalman Observer

Precise motion control requires high-accuracy and high- bandwidth feedback speed information, often calculated by direct measurement of the rotor position available through the incremental encoder equipping the drive. The resolution of the encoder heavily affects the cost of the drive and the accuracy and bandwidth of the calculated speed. The limitations introduced by a low resolution encoder can be partially reduced by a proper speed calculation (or estimation) algorithm, that therefore plays a key role in modern drive systems. In this paper a comparative analysis of state-of-art speed measurement and estimation algorithms suitable for low-resolution incremental encoder equipped drives is presented, aiming at highlighting the specific feature of each one, both from the performance point of view, and from the computational requirements needed for actual implementation. The paper proposes itself as a guide for engineers in the complex choice of the best solution for each application.

/pdf/speed-measurement-algorithms-for-low-resolution-incremental-1lyjsx0kud.pdf

Speed measurement algorithms for low-resolution incremental encoder equipped drives: a comparative analysis

Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the l...

INDEP approach for leakage reduction in nanoscale CMOS circuits

A novel unified model, for conventional copper and futuristic multilayer graphene nanoribbon (MLGNR) interconnects, based on a finite-difference time-domain (FDTD) technique has been proposed in this paper. The performance of quasi-transverse electromagnetic model of interconnects has been exhaustively analyzed for both voltage-mode signaling (VMS) and current-mode signaling (CMS) schemes. The effect of variations in edge roughness and dopant dependent Fermi energy in MLGNR interconnects has been examined. The crosstalk and coupling effects in interconnects have been investigated by incorporating capacitive and inductive interconnect parasitic elements. From the results carried out for 32-nm technology node, it has been observed that for similar dimensions and operating conditions, MLGNR interconnects show a significant performance improvement over the copper interconnects. The results also show that the CMS scheme outperforms VMS scheme at global wire lengths and is very suitable for state-of-the-art chip applications. The proposed model results are in close propinquity with the SPICE results. Furthermore, the FDTD-based model is computationally efficient compared to SPICE.

A Novel Unified Model for Copper and MLGNR Interconnects Using Voltage- and Current-Mode Signaling Schemes

As CMOS technology continues to scale down, leakage currents and interconnection noise will become increasingly large due to the effects of electron tunnelling, short channel effects, coupling capacitance and other factors. Managing these factors by developing better circuits and processes is vital to the continuous success of CMOS technologies in the semiconductor industry. This would require innovative control techniques and architectures in all aspects of CMOS design. Architectural innovation has already lead to renewed industrial interests in asynchronous ICs, which using clockless structure, mitigate the effects of interconnect noise delays and other parasitics in circuits.

Power dissipation and interconnect noise challenges in nanometer CMOS technologies

A wide speed range and high precision position and velocity measurements chip with serial peripheral interface

This paper presents an incremental optical encoder based position and velocity measurements VLSI chip with a serial peripheral interface (SPI). It combines period and frequency countings to provide velocity estimates with good dynamic behavior over a wide speed range. By sensing the velocity of the encoder, it reserves the computational power of a supervisory microcontroller, and subsequently enhances the performance of the total system. Furthermore, multiple copies of the velocity encoder can access the behavior of multiple motors in parallel. It is compact with lower power consumption compared to traditional FPGA implementations. Although designed for use in the control unit of a medical robot with 34-axes and tight space and power constraints, it can be readily used in other applications. It is implemented in a 2P3M 0.5mum CMOS process and consumes 4.82mW power with active area of 0.45mm2.

Incremental Encoder Based Position and Velocity Measurements VLSI Chip with Serial Peripheral Interface

An integrated circuit for controlling a DC motor is disclosed. The integrated circuit includes at least one digital position and speed circuit (DPS) for providing measurements of speed, position, and direction of the motor, the DPS being in signal communication with the motor for receiving a pair of signals having a quadrature relationship; and at least one programmable gain amplifier (PGA) electrically coupled to the motor, the PGA being configured to receive a feedback signal indicative of current flowing through the motor and to apply a second signal to the motor for adjusting the speed of the motor; and at least two analog-to-digital converters (A/D), one A/D being used to quantize the output of the PGA for an off-chip processor; and another A/D to provide motor reference position from an analog sensor, such as a potentiometer; and at least two digital-to-analog converters (D/A), one D/A used to set the motor voltage; and another D/A used to set the motor current limit. The integrated circuit can be incorporated into a larger motor control loop which further includes a summing amplifier for providing the feedback signal to the motor that is indicative of current flowing through the motor; a buffer amplifier electrically for sensing the output current of the motor, and a processor for providing control signals to the system monolithic module and for receiving the measurements of speed, position, and direction of the motor.

Adaptive and reconfigurable system for dc motor control

This paper presents the design of an adaptive hysteretic comparator optimized for noisy environment. It features an input rail-to-rail opamp which uses feedback networks to set varying hysteretic thresholds while maintaining a constant hysteretic band for increased noise immunity and stability. The chip which can resolve up to 9 bits consumes a total power of 3.8 mW and takes an active area of 0.021 mm2 in a 2P3M 0.5 mum CMOS process with 20 ns propagation delay.

Adaptive hysteretic comparator with opamp threshold level setting

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