Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU)---deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs (caches, out-of-order execution, multithreading, multiprocessing, prefetching, ...) that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X - 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X - 80X higher. Moreover, using the GPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

pdf/in-datacenter-performance-analysis-of-a-tensor-processing-15fajz1tol.pdf

In-Datacenter Performance Analysis of a Tensor Processing Unit

Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU) --- deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X -- 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X -- 80X higher. Moreover, using the CPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.

/pdf/in-datacenter-performance-analysis-of-a-tensor-processing-4pmp83zqw4.pdf

In this paper we investigate the performance of a technique for face recognition based on the computation of 25 local autocorrelation coefficients. We use a large database of 11,600 frontal facial images of 116 persons, organized in training and test sets, for evaluation. Autocorrelation coefficients are computationally inexpensive, inherently shift-invariant and quite robust against changes in facial expression. We focus on the difficult problem of recognizing a large number of known human faces while rejecting other, unknown faces which lie quite close in pattern space. A multiresolution system achieves a recognition rate of 95%, while falsely accepting only 1.5% of unknown faces. It operates at a speed of about one face per second. Without rejection of unknown faces, we obtain a peak recognition rate of 99.9%. The good performance indicates that local autocorrelation coefficients have a surprisingly high information content.

Face recognition system using local autocorrelations and multiscale integration

The Spert-II fixed point vector microprocessor system performs training and recall faster than commercial workstations for neural networks used in speech recognition research. We have packaged a prototype full custom vector microprocessor, TO, as the Spert-II (Synthetic Perceptron Testbed II) workstation accelerator system. We originally developed Spert-II to accelerate multiparameter neural network training for speech recognition research. Our speech research algorithms constantly change. Also, neural nets are often integrated with other tasks to form complete applications. We thus desired a general purpose, easily programmable accelerator that could speed up a range of tasks.

/pdf/spert-ii-a-vector-microprocessor-system-2ydsjja8ok.pdf

Spert-II: a vector microprocessor system

SYNAPSE: a neurocomputer that synthesizes neural algorithms on a parallel systolic engine

The analysis of today’s neural paradigms brings to light a set of elementary compute-intensive algorithmic strings which are shared by all neural models and, thus, make sense to be implemented in hardware. 2-D arrays composed of a specific VLSI Neural Signal Processor MA 16 that integrates these elementary strings as hard-wired functional blocks present a favourable solution to the architectural problem of mapping neural parallelity and adaptivity into silicon. The proposed neurocomputer concept is sizeable independently to the applicational domain in terms of processing power, memory size and flexibility, and is designed for throughputs that enable the user to access real-world applications in reasonable time. At the chip site, throughput rates of the order of 500 MC/sec (1 Connection = 16 bit) are achievable with 1μm CMOS technology. 2-dimensional systolic arrays composed of 16x16 MA16 chips will allow for processing of 128 GC/sec.

Design of a 1st Generation Neurocomputer

The architecture and implementation of a Software Defined Radio (SDR) multi-standard baseband processor are presented. As the first representative of a new SDR baseband family, the X-GOLDTM SDR20 has been successfully designed and fabricated in a 65nm CMOS process. The physical layer signal processing for GSM, EDGE, GPRS, UMTS, HSPA, GMR1-3G, and LTE can be implemented in software on this single-chip device. Respective GSM, UMTS and LTE lab demonstrations have proven the competitiveness of this SDR approach.

Architecture and implementation of a Software-Defined Radio baseband processor

whereas virtual round-table conferencing needs at the sender’s side to find a person’s head, cut it from the background, code it and at the receiver’s side to decode and insert it at the round-table by means of geometric transformations (figure below shows virtual round table) Hence, a vision processor has to support image processing, coding/decoding and 3D graphics Accordingly, a representative body of algorithms from these 3 vision fields was analysed with respect to computational power, elementary instructions and data types needed It was found that scalar, vector and matrix constitute the main data types, and a set of 205 visionbased instructions for vector and matrix types was defined Architectural studies led to a parallel array of 16 processing elements (PE) executing the vision instructions on vector and matrix data, as well as to special cache architectures adapted to the new data types For decoding of instructions, a set of controllers had to be introduced that would deliver control bits to the amount of what full-fledged general-purpose processors use to generate, but at a decade lower power level Finally, starting off from the OAK DSP and its Ccompiler, a programming model extending C by some vision based semantics, but keeping the C syntax was thought to be adequate for the user It is the set of 205 application-specific instructions and its computing and memory architecture that make the vision processor a generic one (see [1] for recent alternatives) In the following, only the functional highlights are reported

A 53-GOPS programmable vision processor for processing, coding-decoding and synthesizing of images

New generations of automobiles will include driver assistance systems requiring powerful, low-cost processors to handle video/camera applications and to enable fast, convenient application development. Here, the Corporate Research Division of Infineon Technologies is working on a 100 GOPS vehicle vision platform, which consists of a fully programmable, general purpose vision processor, a convenient software environment based on "C" and the integration of advanced application software. The paper motivates Infineons' approach to vehicle vision systems, presents a brief description of the vision processor, and explains, as examples for application integration, a contour-based approach for an "overtake-checker" and a "door-opener" assistant.

A 100 GOPS vision platform for intelligent vehicles

A circuit for logic devices comprises serially switched part circuits, each having a capacitor and clock signal input (303), a common connection (304) and an ohmic resistance (310-312) between the input and connection. Each resistance is adjusted to give an adjustable delay for the signal reaching the connection depending on this and the capacitance.

Circuit for logic devices comprises part circuits having capacitors, resistances and clock signal inputs with individual delay adjustment

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