This paper presents a brief review of some analog hardware implementations of neural networks. Several criteria for the classification of general neural networks implementations are discussed and a taxonomy induced by these criteria is presented. The paper also discusses some characteristics of analog implementations as well as some trade-offs and issues identified in the work reviewed. Parameters such as precision, chip area, power consumption, speed and noise susceptibility are discussed in the context of neural implementations. A unified review of various "VLSI friendly" algorithms is also presented. The paper concludes with some conclusions drawn from the analysis of the implementations presented.

Neural networks in analog hardware--design and implementation issues.

Results from a neural-network trigger based on the digital MA16 chip of Siemens are reported. The neural trigger has been applied to data from the WA92 experiment, looking for beauty particles, which have been collected during a run in which a neural trigger module based on Intel's analog neural chip ETANN operated, as already reported. The MA16 board hosting the chip has a 16-bit I O precision and a 53-bit precision for internal calculations. It operated at 50 MHz, yielding a response time for a 16 input-variable net of 3 μs for a Fisher discriminant (1-layer net) and of 6 μs for a 2-layer net. Results are compared with those previously obtained with the ETANN trigger.

/pdf/results-from-a-ma16-based-neural-trigger-in-an-experiment-3l8pm7f46k.pdf

Results from a MA16-based neural trigger in an experiment looking for beauty

http://inspirehep.net/record/888386/files/thesis-98-016.pdf

The Hardware Track Finder Processor in CMS at CERN

Two novel neural chips SAND (Simple Applicable Neural Device) and SIOP (Serial Input-Operating Parallel) are described. Both are highly usable for hardware triggers in particle physics. The chips are optimized for a high input data rate at a very low cost basis. The performance of a single SAND chip is 200 MOPS due to four parallel 16 bit multipliers and 40 bit adders working in one clock cycle. The chip is able to implement feedforward neural networks, Kohonen feature maps and radial basis function networks. Four chips will be implemented on a PCI-board for simulation and on a VME board for trigger and on- and off-line analysis. For small sized feedforward neural networks the bit-serial neuro-chip SIOP may lead to even smaller latencies because each synaptic connection is implemented by its own bit serial multiplier and adder.

Neural network chips for trigger purposes in high energy physics

A neural-network trigger has been developed for secondary vertex detection in the WA92 experiment at CERN, looking for the production of beauty particles. The module includes the Intel analog ETANN chip and the Siemens digital (16-bit I/O) MA 16 microprocessor, working independently. The experimental trigger results have already been presented elsewhere. Since this represents the first application of a neural trigger in an high energy physics experiment, we describe here in some detail its hardware and software structure. Specifics are given on the utilization of the ETANN chip, caring about the stability problems associated with its analog nature, and of the MA 16 chip, for which this also represents the first stand-alone application.

Hardware and software structure of a neural network trigger based on the ETANN and MA16 chips

Results from a neural-network trigger based on the digital MA16 chip of Siemens are reported. The neural trigger has been applied to data from the WA92 experiment, looking for beauty particles, which have been collected during a run in which a neural trigger module based on Intel’s analog neural chip ETANN operated, as already reported. The MA16 has a precision of 16 bits for input variables, 16 bits for weights, 16 bits for scalar multipliers modifying the transfer function shape, 47 bits for thresholds, 53 bits for internal calculations, 38 bits for the output. Of the latter only 16 bits are used in the MA16 board, as input to the transfer function inplemented on 16-bit addressable EPROM’s. The MA16 board operated at 50 MHz, yielding a response time for a 16 input variable net of 3 μs for a Fisher discriminant (1-layer net) and of 6 μs for a 2-layer net. Results are compared with those previously obtained with the ETANN trigger.

/pdf/results-from-a-neural-trigger-based-on-the-ma16-pg6mh178kv.pdf

Results from a neural trigger based on the ma16 microprocessor

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Results from a MA16-based neural trigger in an experiment looking for beauty

Results from a neural trigger based on the ma16 microprocessor

Hardware and software structure of a neural network trigger based on the ETANN and MA16 chips