In this paper, we present a simulation study, using ATLAS-2D, of analog circuit performance metrics for the dual-material gate (DMG) MOSFETs in Part I. Part II focuses on the impact of double-layer gate stack architecture on the analog performance and fT-gain relationship of the silicon-on-nothing MOSFETs with and without DMG. The simulation results in Part I demonstrate that, out of the several combinations in DMG MOSFET design studied, the DMG device with an LM1/L ratio of frac12 amalgamates the advantages of using a high metal workfunction gate M1 and a low metal workfunction gate M2 in the most efficient manner. An increase in early voltage and a reduced output conductance from the DMG MOSFET design are the driving forces for the observed performance improvement.

Dual Material Double-Layer Gate Stack SON MOSFET: A Novel Architecture for Enhanced Analog Performance—Part I: Impact of Gate Metal Workfunction Engineering

The synthesis of tungsten silicides by self-propagating combustion has been successfully accomplished under the influence of an electric field Materials with starting composition ranging from 6 to 30 wt % Si were investigated by the method of field-activated combustion synthesis (FACS) A threshold field value was required to initiate a self-sustaining wave; the threshold value depended on composition It was shown that the level of the applied field can influence the mechanism of silicide formation The silicide W 5 Si 3 could be formed only at relatively high field values while WSi 2 can be formed at any field The effect of the field on the silicide formation is discussed in terms of its role in liquid phase formation

The influence of an electric field on the mechanism of combustion synthesis of tungsten silicides

We report a study of the formation of tungsten silicide at the W-Si interface, induced by multipulse (up to 300 shots) XeCl excimer-laser irradiation of W(150 nm)/Si and W(500 nm)/Si samples. Laser fluences ranging from 0.6 to 1.8 J/cm2 were used. After laser treatment the samples were examined by different diagnostic techniques: Rutherford backscattering spectrometry, X-ray scattering, resistometry, and surface profilometry. Numerical computations of the evolution and depth profiles of the temperature in the samples as a consequence of a single 30 ns laser pulse were performed as well. The results indicate that it is possible to obtain a tungsten silicide layer at the W-Si interface at quite low fluences. The layer thickness increases with the number of laser pulses. Complete reaction of the 150 nm thick W film with silicon was obtained at the fluence of 1.2 J/cm2 between 30 and 100 laser pulses and at 1.5 J/cm2 after 30 laser pulses. The sheet resistance of these silicides was 5–10 Ω. At the used fluences for the 500 nm thick W film only the onset of silicide synthesis at the W-Si interface was observed.

Tungsten silicide formation by XeCl excimer-laser irradiation of W/Si samples

The effect of DC bias on the sputter-deposition of W and W-Al on GaAs substrates was investigated. By applying a negative bias to the substrate, the concentration of impurities in the metals and at the interface, such as oxygen, was reduced, and the characteristics of the Schottky contact were improved with respect to the barrier height, the n-value and the uniformity. These results are explained by the reverse sputtering effect for the substrate. This technique was applied to the gate formation of GaAs MESFETs, and the uniformity of the threshold voltage distribution within a 2-inch wafer was much improved.

Effect of Bias Sputtering on W and W-Al Schottky Contact Formation and its Application to GaAs MESFETs : III-V Compound Semiconductors Devices and Materials( Solid State Devices and Materials 1)

A fabrication process of 0.5 mu m gate GaAs-MESFETs combined with high-dielectric-constant thin-film capacitors was investigated. A buried p layer (BP) is employed to suppress short-channel effects by using the carbon ion implantation technique. These BP-MESFETs have a self-aligned n+ asymmetric lightly doped drain (LDD) structure to realize low source resistance and high drain breakdown voltage. The planarization technique was adopted to deposit an Au overlayer on top of the 0.5 mu m WSi gate to improve the high-frequency performance by reducing the gate resistance. These BP-MESFETs have a high K value, over 230 mA V-2 mm-1, and a maximum frequency of oscillation fmax of 60 GHz with an n+ asymmetric structure. We also have developed high-dielectric-constant SrTiO3 thin-film capacitors by using the low-temperature RF sputtering method. These SrTiO3 films have high epsilon rs over 100, and low leakage current density, under 1*10-6 A cm-2 at 1 MV cm-1. By using this SrTiO3 capacitor for the bypass capacitors of the MMIC, we can reduce the pin counts of the MMIC and will be able to realize a shrinkage of the total size of the RF unit of a cellular telephone. We have fabricated the front-end IC of a cellular telephone using this newly developed process technology, and can achieve low power consumption.

http://iopscience.iop.org/article/10.1088/0268-1242/10/11/017/pdf

A new GaAs MMIC process technology using 0.5 mu m gate asymmetric LDD structure GaAs BP-MESFETs combined with high-dielectric-constant thin-film capacitors

A co-sputtering process is characterized which allows the deposition of WSi0.4 layers for Schottky gates of GaAs self-aligned MESFETs. The process parameters were optimized to yield films with low stress, good adhesion and a high interface stability during 800°C n+ implant activation anneal. The good diffusion barrier properties of the Schottky metal can be attributed to the amorphous nature of the film. This implies a natural explanation of the optimum film composition. Employing various analytical methods the gate metal/GaAs interface was characterized after 800°C anneal. I−V diode measurements were performed to obtain contact electrical properties such as barrier height and ideality factor. MESFETs with different channel implants down to 10 keV were fabricated to confirm the good stability of the Schottky contact.

WSix refractory gate metal process for GaAs MESFETs

A GaAs MESFET fabrication process based on self-aligned WSi gates with gatelengths down to 0.5 μm is described. A buried p-layer is employed to suppress short-channel effects. The shallow FET channels are connected to the deeper implants of the ohmic source and drain contacts by means of an intermediate-dose “lightly-doped drain” (LDD) implant. Owing to a planarization concept which allows the use of a low-resistance Au overlayer on top of the high resistivity WSi gates, the process yields FETs with excellent high-frequency performance. This is proved by transit frequencies ƒ t exceeding 30 GHz, maximum frequencies of oscillation ƒ max of typically 100 GHz, and a noise figure NFmin of 1.0 dB at 12 GHz (nominal gatelength 0.5 μm). FETs with three different threshold voltages are fabricated. All three types of transistors have transconductances of 300 mS/mm or above. This combination of properties makes the technology suitable for the realization of digital as well as microwave circuits.

A self-aligned GaAs MESFET process with WSi gates for analog and digital applications

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WSix refractory gate metal process for GaAs MESFETs

A self-aligned GaAs MESFET process with WSi gates for analog and digital applications