Munir D. Naeem
IBM
39 Papers
406 Citations
Munir D. Naeem is an academic researcher from IBM. The author has contributed to research in topics: Etching (microfabrication) & Layer (electronics). The author has an hindex of 9, co-authored 39 publications. Previous affiliations of Munir D. Naeem include Infineon Technologies & Rensselaer Polytechnic Institute.
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Papers
Plasma-etching processes for ULSI semiconductor circuits
Michael D. Armacost,Peter D. Hoh,Richard Wise,W. Yan,Jeffrey J. Brown,J. H. Keller,George A. Kaplita,Scott Halle,K. P. Muller,Munir D. Naeem,S. Srinivasan,Hung Y. Ng,M. Gutsche,A. Gutmann,B. Spuler +14 more
TL;DR: An overview is presented of plasma-etching processes used in the fabrication of ULSI (ultralarge-scale integrated) semiconductor circuits, with emphasis on work in the authors' facilities.
79
Patent
Microscope specimen holder and grid arrangement for in-situ and ex-situ repeated analysis
Munir D. Naeem
- 08 May 1998
TL;DR: In this article, the alignment aid of the grid may be a notch or an aperture; the reference aid of a specimen holder may be raised surface or a pin; and a reference aid, located in the opening of the specimen holder, can be engaged to orient the grid in a single position within the opening.
45
Patent
Method of reducing RIE lag for deep trench silicon etching
Munir D. Naeem,Gangadhara S. Mathad,Byeong Y. Kim,Stephan Kudelka,Brian S. Lee,Heon Lee,E. Morales,Young-Jin Park,Rajiv M. Ranade +8 more
- 31 May 2000
TL;DR: In this paper, a method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio was described.
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Dual stress liner enhancement in hybrid orientation technology
Christopher D. Sheraw,Min Yang,David M. Fried,Gregory Costrini,Thomas S. Kanarsky,Woo-Hyeong Lee,Victor Chan,Massimo V. Fischetti,Judson R. Holt,L. Black,Munir D. Naeem,Siddhartha Panda,L. Economikos,J. Groschopf,A. Kapur,Yujun Li,Renee T. Mo,A. Bonnoit,D. Degraw,Scott Luning,Dureseti Chidambarrao,Xinhui Wang,Andres Bryant,D. Brown,Chun-Yung Sung,Paul D. Agnello,Meikei Ieong,Shih-Fen Huang,X. Chen,Mukesh Khare +29 more
- 14 Jun 2005
TL;DR: Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown [110] bulk silicon.
37
Patent
Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing
Munir D. Naeem,Stuart M. Burns,Nancy Anne Greco,Greco Steve,Virinder Singh Grewal,Ernest N. Levine,Narita Masaki,Bruno Spuler +7 more
- 20 Jun 1997
TL;DR: In this paper, the authors proposed a method in a plasma processing chamber for etching through a selected portion of a layer stack consisting of a metallization layer, a first barrier layer, and a photoresist layer.
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