Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods and systems for utilizing design data in combination with inspection data

A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Integrated circuit layout design methodology with process variation bands

Disclosed is a method for determining an overlay error between at least two layers in a multiple layer sample. An imaging optical system is used to measure a plurality of measured optical signals from a plurality of periodic targets on the sample. The targets each have a first structure in a first layer and a second structure in a second layer. There are predefined offsets between the first and second structures. A scatterometry overlay technique is then used to analyze the measured optical signals of the periodic targets and the predefined offsets of the first and second structures of the periodic targets to thereby determine an overlay error between the first and second structures of the periodic targets.

Apparatus and methods for detecting overlay errors using scatterometry

Methods and systems are disclosed to inspect a manufactured lithographic mask, to extract physical mask data from mask inspection data, to determine systematic mask error data based on differences between the physical mask data and mask layout data, to generate systematic mask error parameters based on the systematic mask error data, to create an individual mask error model with systematic mask error parameters, to predict patterning performance of the lithographic process using a particular mask and/or a particular projection system, and to predict process corrections that optimize patterning performance and thus the final device yield.

System and method for mask verification using an individual mask error model

Various methods and systems for determining a position of inspection data in design data space are provided. One computer-implemented method includes determining a centroid of an alignment target formed on a wafer using an image of the alignment target acquired by imaging the wafer. The method also includes aligning the centroid to a centroid of a geometrical shape describing the alignment target. In addition, the method includes assigning a design data space position of the centroid of the alignment target as a position of the centroid of the geometrical shape in the design data space. The method further includes determining a position of inspection data acquired for the wafer in the design data space based on the design data space position of the centroid of the alignment target.

Methods and systems for determining a position of inspection data in design data space

An overlay method for determining the overlay error of a device structure formed during semiconductor processing is disclosed. The overlay method includes producing calibration data that contains overlay information relating the overlay error of a first target at a first location to the overlay error of a second target at a second location for a given set of process conditions. The overlay method also includes producing production data that contains overlay information associated with a production target formed with the device structure. The overlay method further includes correcting the overlay error of the production target based on the calibration data.

Overlay metrology and control method

Various computer-implemented methods are provided. One method for evaluating reticle layout data includes generating a simulated image using the reticle layout data as input to a model of a reticle manufacturing process. The simulated image illustrates how features of the reticle layout data will be formed on a reticle by the reticle manufacturing process. The method also includes determining manufacturability of the reticle layout data using the simulated image. The manufacturability is a measure of how accurately the features will be formed on the reticle. Also provided are various carrier media that include program instructions executable on a computer system for performing a method for evaluating reticle layout data as described herein. In addition, systems configured to evaluate reticle layout data are provided. The systems include a computer system and a carrier medium that includes program instructions executable on the computer system for performing method(s) described herein.

Methods, systems, and carrier media for evaluating reticle layout data

Computer-implemented methods for detecting defects in reticle design data are provided. One method includes generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process. The method also includes generating second simulated images using the first simulated image. The second simulated images illustrate how the reticle will be printed on a wafer at different values of one or more parameters of a wafer printing process. The method further includes detecting defects in the reticle design data using the second simulated images. Another method includes the generating steps described above in addition to determining a rate of change in a characteristic of the second simulated images as a function of the different values. This method also includes detecting defects in the reticle design data based on the rate of change.

Computer-implemented methods for detecting defects in reticle design data

Disclosed are apparatus and methods for monitoring a characteristic associated with a product feature on a semiconductor product. A proxy target formed from at least one substructure that corresponds to a product feature is provided. The substructure is not individually resolvable by an optical tool. A characteristic of the proxy target is determined based on optically monitoring the proxy target using the optical tool. Based on the determined characteristic of the proxy target, it is then determined whether the corresponding product feature has a characteristic that is within a predetermined specification or whether a process parameter used to fabricate such product feature is within a predetermined specification. In a specific embodiment, the characteristic of the corresponding product feature includes a shape parameter and a position parameter.

Apparatus and methods for optically monitoring the fidelity of patterns produced by photolitographic tools

A complete evaluation of the optical proximity effects (OPE) and of their corrections (OPC) requires a quantitative description of two-dimensional (2D) parameters, both at resist- and at reticle-level. Because the 2D behaviour at line-ends and at line-corners can become a limiting factor for the yield, it should be taken into account when characterising a process, just as the CD- and pitch-linearity are already kept under control. This implies the measurement of 2D-metrics in a precise way. We used an SEM Image Analysis tool (ProDATA SIAM) to define and measure various OPC-relevant metrics for a C013 process. 

For the METAL (M1) process, we show that the overlap between line-ends of M1-trenches and underlying nominal contacts is a relevant metric to describe the effectiveness of hammerheads. Moreover, it is an interesting metric to combine with the CD process window. For the GATE process, we demonstrate that for a given set of metrics there is a degree of OPC aggressiveness beyond which it is not worth to go. We considered both line-end shortening (LES) and corner rounding affecting the poly linewidth close to a contact pad, and this on various logic circuits having received different degrees of fragmentation. Finally the knowledge of the actual line-end contour on the reticle allows one to simulate separately the printing effect of that area loss at reticle line-ends. The area loss measured by comparing the extracted contour to the target one is regarded as a combination of pull-back and area loss at corners. For our C013 gate process, and for the 130nm lines at a 1:1.25 duty cycle, those two parameters contribute together to approximetely 40% of the measured LES in the resist. This fact raises the question of specifications on 2D reticle parameters. We also find a linear correlation between the area loss at reticle line-end corners and the corresponding increase of LES on the wafer, which suggests a way towards putting specifications on the reticle line-ends.

Assessment of OPC effectiveness using two-dimensional metrics

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