Advancements in information technology is contributing to the excessive rate of big data generation recently. Big data refers to datasets that are huge in volume and consumes much time and space to process and transmit using the available resources. Big data also covers data with unstructured and structured formats. Many agencies are currently subscribing to research on big data analytics owing to the failure of the existing data processing techniques to handle the rate at which big data is generated. This paper presents an efficient classification and reduction technique for big data based on parallel generalized Hebbian algorithm (GHA) which is one of the commonly used principal component analysis (PCA) neural network (NN) learning algorithms. The new method proposed in this study was compared to the existing methods to demonstrate its capabilities in reducing the dimensionality of big data. The proposed method in this paper is implemented using Spark Radoop platform.

An effective classification approach for big data with parallel generalized Hebbian algorithm

We are living in the 21 st century, an era of acquiring necessity in one click. As we, all know that technology is continuously reviving to stay ahead of advancements taking place in this world of making things easier for mankind. Technology has been putting his part in introducing different projects as we have used the field programmable gate arrays (FPGAs) development board of low cost and programmable logic done by the new evolvable cyclone software is optimized for specific energy based on Altera Cyclone II (EP2C5T144) through which we can control the speed of any electronic device or any Motor Control IP product targeted for the fan and pump. Altera Cyclone FPGAs’ is a board through which we can monitor the speed and direction of the DC motor. As we know how to make understand, dynamic analog input using an A-to-D convertor and we know how to create pulse width modulation (PWM) output with FPGA. Therefore, by combining these two functions we can create an FPGA DC motor controller. Our paper is divided into three parts: First, all of us will attempt to imitate the issue and can try to look for its answer. Secondly, we will try to verify the solution for real-time. In addition, in the last step, we will verify the solution on the real-time measurements.

/pdf/monitoring-and-controlling-the-speed-and-direction-of-a-dc-3jh274c48j.pdf

Monitoring and controlling the speed and direction of a DC motor through FPGA and comparison of FPGA for speed and performance optimization

Photovoltaic (PV) inverters have been widely used in solar energy to change the direct current (DC) voltage of PV panels to the grid alternating current (AC) voltage. They are comprised of DC-DC section for maximum power point tracking (MPPT) and DC-AC part to provide required output AC voltage. This paper provides a unique configuration that integrates both sections in one part. A Z-source multilevel inverter is proposed based on Z-source networks and reversing voltage (RV) multilevel inverter. The Z-source network can be used to increase the level of the input voltages and MPPT as well. In addition, the prop used topology uses multilevel topology to accommodate more DC inputs and benefit from features of multilevel level inverters in AC output. Moreover, using Z-source network can minimize equated monthly installment (EMI) due to the lower stress on the semiconductor switches. Finally, a seven level topology is designed and simulated to show the performance of proposed topology.

/pdf/z-source-reversing-voltage-multilevel-inverter-for-2pgpe1xf.pdf

Z-source reversing voltage multilevel inverter for photovoltaic applications with inherent voltage balancing

Total harmonic distortion (THD) is<span style="font-size: 10.0pt; font-family: 'Times New Roman',serif; mso-fareast-font-family: 'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA;" lang="EN-US"> a key index used to measure the quality of output waveforms in multilevel inverters. In this paper the THD is investigated and compared between two modulation methods; selective harmonic elimination and nearest level control, for 13-level transistor clamped H-bridge (TCHB) inverter. The selected TCHB topology employs a reduced number of DC sources and switches compared with other conventional multilevel inverters, which helps to reduce the size and cost of the inverter. The performance of both modulation methods has been validated through simulations using MATLAB/Simulink. The results show that for selective harmonic elimination, the 13-level output exists for a narrow range of modulation index, M (0.687≤M≤0.694),while for nearest level control method, the 13-level output exists for a wider range of M (M≥0.917), which means the 13-level output exists for different ranges of  for both methods. The THD obtained from both methods fulfills the IEEE Std 519-2014 standard of harmonics. Nearest level control method is conceptually simple and produces better THD results compared with selective harmonic elimination method.distortion (THD) is<span style="font-size: 10.0pt; font-family: 'Times New Roman',serif; mso-fareast-font-family: 'Times New Roman'; mso-ansi-language: EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA;" lang="EN-US"> a key index used to measure the quality of output waveforms in multilevel inverters. In this paper the THD is investigated and compared between two modulation methods; selective harmonic elimination and nearest level control, for 13-level transistor clamped H-bridge (TCHB) inverter. The selected TCHB topology employs a reduced number of DC sources and switches compared with other conventional multilevel inverters, which helps to reduce the size and cost of the inverter. The performance of both modulation methods has been validated through simulations using MATLAB/Simulink. The results show that for selective harmonic elimination, the 13-level output exists for a narrow range of modulation index,  (), while for nearest level control method, the 13-level output exists for a wider range of  (), which means the 13-level output exists for different ranges of  for both methods. The THD obtained from both methods fulfills the IEEE Std 519-2014 standard of harmonics. Nearest level control method is conceptually simple and produces better THD results compared with selective harmonic elimination method

Comparison between selective harmonic elimination and nearest level control for transistor clamped H-bridge inverter

Received May 27, 2022 Revised Aug 13, 2022 Accepted Sep 30, 2022 The use of multi-level inverter (MLI) technologies in high-power, mediumvoltage energy regulation has been more popular in recent years. Despite the fact that the multilayer inverter has a lot of benefits, it has certain disadvantages in the layer of higher levels due to the enormous number of semiconductor switches that it employs in its construction. This may result in the inverter being of a huge size and costing a lot of money, as well as a significant rise in losses. As a result, the new MLI is suggested to minimize the number of switches in order to alleviate these challenges. This article describes a cascaded multilevel inverter with lower devices. The suggested cascaded multilevel inverter is intended for use in minimizing total harmonic distortion (THD), as shown in MATLAB/Simulink by the graph. Multilevel inverters benefit from the switching pattern of semiconductor switches, which may be used to improve their overall performance. This approach lowers the switching loss while simultaneously increasing the efficiency. In order to validate the suggested approach, simulations are carried out using the MATLAB/Simulink programming environment.

Bulletin of Electrical Engineering and Informatics

The Space Vector Modulation SVM technique has won large acceptance for AC drive applications. However the utilization of multilevel inverters connected with SVM by Digital signal processor (DSP) raise the intricacy of control algorithm or computational load, increases of the obtaining distortions output voltage. The development of SVM in multilevel inverters may offer higher numbers of switching vectors for acquiring further enhancements of output voltage performances and implement by using Field Programmer Gate Array (FPGA), investigate lower Total Hormonic Distortion (THD). This paper reports the performance evaluation of SVM for five-level of Cascaded H-Bridge Multilevel Inverter CHMI using MATLAB/Simulink, which is sampled at the minimum sampling time, i.e. DT = 5 μs. The switching signals for driving insulated gate bipolar transistor (IGBTs) which are stored in MATLAB workspaces, are then used to be programmed in FPGA using a Quartus II software. Which can be stated the lower THD of the simulation result is about 14.48% for five-level CHMI and experiment result is about 14.31% for five-level CHMI at modulation index M_i=0.9. The error percentage between the simulation results and experimental results of the fundamental output voltage in SVM is small which is approximately less than 1 %.

https://ijpeds.iaescore.com/index.php/IJPEDS/article/download/20412/13161

Implementation of SVM for five-level cascaded H-Bridge multilevel inverters utilizing FPGA

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Implementation of SVM for five-level cascaded H-Bridge multilevel inverters utilizing FPGA