This paper introduces an efficient reconfigurable, multiple voltage gain switched-capacitor dc-dc buck converter as part of a power management unit for wearable electronics. The proposed switched-capacitor converter has an input voltage of 0.6 V to 1.2 V generated from an energy harvesting source. The switched-capacitor converter utilizes pulse frequency modulation to generate multiple regulated output voltage levels, namely 1 V, 0.8 V, and 0.6 V based on two reconfigurable bits over a wide range of load currents from 10 $\mu\text{A}$ to 800 $\mu\text{A}$ . The switched-capacitor converter is designed and fabricated in 65-nm low-power CMOS technology and occupies an area of 0.493 mm2. The design utilizes a stack of MIM and MOS capacitances to optimize the circuit area and efficiency. The measured peak efficiency is 80% at a load current of 800 $\mu\text{A}$ and regulated load voltage of 1 V.

An Efficient Switched-Capacitor DC-DC Buck Converter for Self-Powered Wearable Electronics

Computer vision is one of the most active research fields in information technology today. Giving machines and robots the ability to see and comprehend the surrounding world at the speed of sight creates endless potential applications and opportunities. Feature detection and description algorithms can be indeed considered as the retina of the eyes of such machines and robots. However, these algorithms are typically computationally intensive, which prevents them from achieving the speed of sight real-time performance. In addition, they differ in their capabilities and some may favor and work better given a specific type of input compared to others. As such, it is essential to compactly report their pros and cons as well as their performances and recent advances. This paper is dedicated to provide a comprehensive overview on the state-of-the-art and recent advances in feature detection and description algorithms. Specifically, it starts by overviewing fundamental concepts. It then compares, reports and discusses their performance and capabilities. The Maximally Stable Extremal Regions algorithm and the Scale Invariant Feature Transform algorithms, being two of the best of their type, are selected to report their recent algorithmic derivatives.

Recent Advances in Features Extraction and Description Algorithms: A Comprehensive Survey

Digital images are being used as a prominent carrier of visual information in this age of digitization. Images become more and more omnipresent in everyday life. The images can be easily manipulated due to the accessibility of many internet tools and advanced software. Previously many techniques have been developed to authenticate the images. But all the previous techniques have high dimension of feature vectors. Here, a low dimensional DCT and DWT based features have been introduced to authenticate the images. In this work, we are dealing with both the passive forgery (splicing and copy-move) simultaneously. Features are extracted through image statistics and pixel correlation from DCT and DWT domain. Ensemble classifier has been selected for training and testing. The classifier classifies whether the given images are forged or authentic. Further, it also classifies the forgery in spliced or copy-move. If there is copy-move, the proposed work also perform the region detection using a novel key-point based method. The proposed model gives good detection accuracy and high generalization capability which is independent of image formats. Experimental results demonstrate the performance of proposed work against different post-processing operations like scaling, rotation, and Gaussian noise. Also, the comparative results against different existing methods show the effectiveness of the proposed model.

Low dimensional DCT and DWT feature based model for detection of image splicing and copy-move forgery

As the security threat and crime rate have been increased all over the globe, the video surveillance system using closed-circuit television (CCTV) has become an essential tool for many security-related applications and is widely used in many areas as a monitoring system. However, most of the data collected by the video surveillance system is used as evidence of objective data after crime and disaster have occurred. And, often time, video surveillance systems tend to be used in a passive manner due to the high cost and human resources. The video surveillance system should actively respond to detect crime and accidents in advance through real-time monitoring and immediately transmit data in case of an accident. This study proposes developing an intelligent video surveillance system that can actively monitor in real-time without human input. In solving the problems of the existing video surveillance system, deep learning technology will be carried through the data processing model design to visualize data for crime detection after building an artificial intelligence server and video surveillance camera. In addition, this design proposes an intelligent surveillance system to quickly and effectively detect crimes by sending a video image and notification message to the web through real-time processing.

Design of an intelligent video surveillance system for crime prevention: Applying deep learning technology

This paper presents a power management unit (PMU) architecture for multi-source energy harvesting system in wearable devices. The energy harvesting system utilizes a thermal and vibration harvesters as energy sources. In addition, the PMU is designed to control the harvested energy as well as to manage the power delivered to an ECG processor. Further, the PMU generates different signals to enable and disable the processor depending on the available energy. The ECG processor analyzes ECG signals and predicts ventricular arrhythmia (VA). The ECG processor is a multi-voltage design that uses a 0.6V for the processing core and a 1V for the SRAM. Simulation results of the PMU shows the operation of the ECG processor at different energy states in different modes of operation. The proposed architecture could help wearable electronics to run at their optimum energy point to increase their life time.

Power management unit for multi-source energy harvesting in wearable electronics

This paper presents a novel implementation of the Maximally Stable Extremal Regions (MSER) detector on system-on-chip (SoC) using 65nm CMOS technology. The novel SoC was developed following the Application Specific Integrated Circuit (ASIC) design flow which significantly enhanced its realization and fabrication, and overall performances. The SoC has very low area requirement (around 0.05 mm2) and is capable of detecting both bright and dark MSERs in a single run, while computing simultaneously their associated regions' moments, simplifying its interfacing with other image algorithms (e.g. SIFT and SURF). The novel MSER SoC is power-efficient (requires 2.25 mW) and memory-efficient as it saves more than 31% of the memory space reported in the state-of-the-art MSER implementation on FPGA, making it suitable for mobile devices. With 256×256 resolution and its operating frequency of 133 MHz, the SoC is expected to have a 200 frames/second processing rate, making it suitable (when integrated with other algorithms in the system) for time-critical real-time applications such as visual surveillance.

A maximally stable extremal regions system-on-chip for real-time visual surveillance

Numerous techniques and algorithms have been developed and implemented, primarily in software, for object tracking, detection and recognition. A few attempts have been made to implement some of the algorithms in hardware. However, those attempts have not yielded optimal results in terms of accuracy, power and memory requirements. The aim of this paper is to explore and investigate a number of possible algorithms for real-time video surveillance, revealing their various theories, relationships, shortcomings, advantages and disadvantages, and pointing out their unsolved problems of practical interest in principled way, which would be of tremendous value to engineers and researchers trying to decide what algorithm among those many in literature is most suitable to specific application and the particular real-time System-on-Chip (SoC) implementation.

Automated real-time video surveillance algorithms for SoC implementation: A survey

DC-DC converters are important building block of most of today's System-on-Chips (SoCs). This is true because the need to modulate the voltage of different parts of the chip to operate at the optimum level is essential to achieve high power efficiency. This paper investigates two topologies of the DC-DC converter that are widely used. The two topologies are Low Dropout regulator and Switched Inductor DC-DC buck converter. The operation for both topologies is explained as well as the advantages and disadvantages of each topology. Spice simulation with 65nm low power foundry process technology is used to compare the two topologies in terms of energy efficiency, settling time, area, and design complexity. Detail study of voltage level conversion and output load current and its impact on efficiency is also reported.

LDO regulator versus switched inductor DC-DC converter

This paper presents a reconfigurable high efficiency Switched Capacitor DC-DC Converter targeting ultra-low power applications. The Switched Capacitor utilizes multiple gains to provide variable output voltage (1V, 0.8V and 0.6V). The design modulates both switching frequency and transistor size depending on the load current in order to minimize the losses associated with the Switched Capacitor. The Switched Capacitor is implemented using 65nm Low Power CMOS process technology, spice simulation shows power efficiency above 65% over a wide range of load current from 10 μA to 1mA. The power efficiency reaches its peak value of 85% at low load current of 500 μA.

Switched capacitor DC-DC converter for ultra-low power applications

Diabetes is characterized by high glucose levels in the blood that result from defects in insulin secretion, or its action, or both, being considered as one of the major contributors of precipitate infirmity and death in non-contagious diseases. Glucose meter is the prevailing technique to determine the glucose level, a technique involving chemical analysis of a sample of the diabetic blood obtained by pricking a finger. Yet, due to the many demerits of the glucose meter, including the pain and the direct contact requirement, many alternatives were proposed in the literature. In this paper, we explore and compare, based on a number of performance metrics, some of those techniques and systems and their compatibility to be implemented for System-on-Chip (SoC) for glucose and health monitoring, which will potentially transform the future of healthcare by enabling proactive personal health care and ubiquitous monitoring of a patient's health profile and condition. A preliminary SoC design for non-invasive glucose monitoring is proposed.

The revolution of glucose monitoring methods and systems: A survey

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