Assertion Based Verification (ABV) is one of the widely used verification technique to enhance the verification quality and reduce the debugging time of complex system-on-chip (SOC) designs in order to speedup the verification process. A verification environment to verify an AMBA-AHB (Advanced High Performance Bus) by using SystemVerilog Assertion (SVA) is presented in this paper as it can easily be turned ON or OFF at any instant during simulation as needed. First the AMBA-AHB is modeled using 3 masters and 4 slaves in verilog language. This design is then verified using SVA binding construct in ModelSim. Binding allows verification engineers to add assertions to design without touching the design files. The different properties of AMBA-AHB and its corner cases properties are verified using ModelSim and the total coverage report of the design is calculated. In this paper, we define the assertions in separate modules and use the BIND SystemVerilog feature to bind the assertion modules to the Verilog RTL modules. Here, we have clear separation between the RTL modules and the assertion modules.

SystemVerilog Assertion Based Verification of AMBA-AHB

Machine learning techniques based on Data Miningare employed for automatic assertion generation in hardwaredigital design verification. This paper presents a new miningtechnique to extract all design properties from simulation traces.The extracted properties cover all possible design assertionseither at system level or Register Transfer Logic (RTL)verification depending on the simulated design level. It canafterwards be tuned or filtered to match a certain desiredabstraction level. The new technique is based on a Breadth-FirstDecision Tree (BF-DT) search algorithm. The innovatedalgorithm maps the input simulation traces to a search tree thatcovers all possible input combinations, and prunes the redundantpaths. The proposed technique is tested against recentlyinnovated mining techniques for some basic digital designfunctions as a proof of concept for the gained efficiency. Themain advantage of the new technique is the possibility to extractall the design properties from the simulation traces achievinghundred-percent coverage in a reasonably efficient time formillions of simulation traces.

Complete Properties Extraction from Simulation Traces for Assertions Auto-generation

This paper introduces a new methodology for digital design properties extraction from simulation traces. The innovated methodology is based on a new data mining technique guided with static analysis of the intended design. The mining engine of the proposed methodology is based on innovated Breadth-First Decision Tree (BF-DT) search algorithm. The data structure of each node in the decision tree is handled to well present sub-space of the input simulation traces data space. Besides, new features are added to BF-DT to enhance its performance in both output sequential assertions and time of search. A new static analysis technique is innovated to extract all the combinational and sequential data dependencies between the digital design signals. The mining engine is guided with these data dependencies to extract complete combinational and sequential design properties relating signals desired to extract properties for and their cone of interest signals. The contributed mining technique has been tested for bit-level designs with different sizes. The design properties generated from the mining engine completely match with all design properties covered in the input simulation traces. Plus, the generated properties are at the highest possible level of abstraction leading to the best coverage for the input data space. The simulation results show that the proposed methodology has proven superior efficiency in extracting bit-level assertions of digital design in a feasible time. The next challenge is to include word-level assertions as well.

https://ieeexplore.ieee.org/iel7/7386534/7392993/07393026.pdf

New methodology for digital design properties extraction from simulation traces

This paper introduces a new methodology for digital design properties extraction from simulation traces. A new Breadth-First Decision Tree (BF-DT) mining algorithm is proposed for complete properties extraction from simulation traces. The new mining engine supports both bit-level and word-level values of different design variables. Static analysis technique is implemented to extract all data dependencies between the digital design variables. New traces regeneration algorithm is proposed to obtain reduced traces for more efficient and easier mining. The mining engine is guided with these data dependencies to extract complete design properties relating target variables desired to extract properties for and their cone of interest feature variables. The contributed mining technique has been tested for different designs with different sizes. The design properties generated from the mining engine completely match with all design properties covered in the input simulation traces. Moreover, the generated properties are at the highest possible level of abstraction leading to the best coverage for the input data space. The simulation results show that the proposed methodology has superior efficiency in extracting both bit-level and word-level complete assertions of digital design in both superior quality and feasible time.

New Methodology for Complete Properties Extraction from Simulation Traces Guided with Static Analysis

Debugging a complex design is not an easy process. The more complex the design is, the more mistakes can be made, while writing an assertion. Regular expressions are widely used for text searching and replacement. Both regular expressions and three-state visual representation can be used simultaneously to validate and debug assertions. This paper presents a new methodology for debugging concurrent assertions based on a three-state visual representation and a new proposed pattern matching model. The proposed pattern matching model uses a new approach to validate assertions. The new approach performs parallel sequence items checking instead of serial checking of each sequence along time. The proposed new methodology assumes that error is just in the assertion and no errors are in the testbench or in the design. Experimental results show how much this methodology is effective that errors are analyzed and fixed within two minutes.

SystemVerilog assertion debugging: A visualization and pattern matching model

System-on-chip designs became complex. As such, tracing complex sequential circuits over many clock cycles is not a simple process any more. Due to that, many mistakes can be made while writing assertions. In this paper, a new effective methodology is proposed to debug errors in an assertion assuming that there is no error in the design or the test bench. The proposed methodology is based on an innovated propagate-and-repeat algorithm, an enhanced mutation model, and a new three-state visual representation. A multi-core processing utilizing an efficient event scheduling engine is used to speed up the methodology analysis time. Experimental results show the efficiency of the proposed methodology in determining the errors in the assertion and on providing more information on design behavior.

System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation

Handle everyday research tasks with reliable, citation-backed results

Your personal Research Agent to handle research tasks with citation-backed results

Popular Tasks used by Researchers

How can I help with your research?

Meet SciSpace

Get more enhanced response by uploading the PDFs you want me to reference.

No relevant PDFs in your library

SciSpace is the AI research assistant for academics. Run systematic literature reviews on 280M+ papers, and write papers with cited sources. Trusted by 1M+ students, PhDs & researchers.

SciSpace | AI for Research

Analyze PDFs

Code & Manuscripts

Funding & Grants

Literature & Patents

Medical & Clinical Data

Systematic Review

Visualize & Present

Web & Data

Build a Google Scholar-like website for your research.

Build a website

Create charts and images for your research

Create a Chart

Write a paper for submission to a journal

Draft a manuscript

Patent Search

Design eye-catching scientific posters in minutes.

Scientific Poster Generation

Systematic Literature Review

One task is running at the moment. Your messages will be shown right after.

Drag and drop or click here to browse

Loved by <highlight>1 million+</highlight> researchers

Extract a list of specific topics and their sources from unstructured text

Topics

Compare and analyze relevant papers that matches with your search

Papers

Get insights from PDFs and bookmarked papers from your library

My library

Recent searches

Try searching for:

Catch AI-generated content in scholarly and non-scholarly content

{ai} Detector

Ai Writer

Get PDF Summaries, highlighted text explanations 

Chat with PDF

Effortlessly create in-text citations and bibliographies in APA and 2,500 other formats

Citation generator

Get explanations, summaries, and answers on academic papers

Ease up your research workflow with {scispace}'s cohort of exciting AI tools

Elevate your academic writing skills and convey your ideas the way you want

Paraphraser

Explore our range of reading and writing tools

Your file is being prepared and should be ready in a few minutes. If it's a large file, it might take a bit longer. You can close this window, and we'll email you the file when it's done.

You have reached a maximum limit of <strong>{limit}</strong> columns in the table. Remove at least <strong>1</strong> column to add or create another one.

Moaz Mostafa

Author Tools

Chat about Author

Papers

System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation

SystemVerilog assertion debugging: A visualization and pattern matching model