An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Catalyst-free growth of (In)GaN nanowires on (001) silicon substrate by plasma-assisted molecular beam epitaxy is demonstrated. The nanowires with diameter ranging from 10 to 50 nm have a density of 1−2 × 1011 cm−2. P- and n-type doping of the nanowires is achieved with Mg and Si dopant species, respectively. Structural characterization by high-resolution transmission electron microscopy (HRTEM) indicates that the nanowires are relatively defect-free. The peak emission wavelength of InGaN nanowires can be tuned from ultraviolet to red by varying the In composition in the alloy and “white” emission is obtained in nanowires where the In composition is varied continuously during growth. The internal quantum efficiency varies from 20−35%. Radiative and nonradiative lifetimes of 5.4 and 1.4 ns, respectively, are obtained from time-resolved photoluminescence measurements at room temperature for InGaN nanowires emitting at λ = 490 nm. Green- and white-emitting planar LEDs have been fabricated and characterized. ...

Catalyst-free InGaN/GaN nanowire light emitting diodes grown on (001) silicon by molecular beam epitaxy.

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias.

Chips having rear contacts connected by through vias to front contacts

A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Through-wafer interconnects for photoimager and memory wafers

We have demonstrated a high-density wiring interposer for 10 GHz 3D packaging using a photosensitive multiblock copolymerized polyimide. This new polyimide can realize micron-sized fine patterns without the pattern shrinkage because of not requiring high-temperature thermal curing. The polyimide has good electric properties such as high breakdown voltage and low dielectric constant. Therefore, it is considered that by introducing this photosensitive polyimide as an insulator of the interposer, a high-performance interposer for LSI packaging can be realized. We confirmed experimentally that the high-density wiring interposer could be fabricated using the polyimide and the gold metal. From time domain reflectometry (TDR) measurement by using a specially prepared 20-/spl mu/m-pitch microwave contact probe, it was found that the characteristic impedance of the stripline is within 55.2 /spl Omega//spl plusmn/11.5 % at the central 10-mm-square area of the interposer.

Ultra wide bandwidth performance of high-density wiring interposer for 3D packaging

A peeling prevention layer for preventing an insulation film and a protection layer from peeling is formed in corner portions of a semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.

Method of manufacturing a semiconductor device with a peeling prevention layer

The present invention provides a semiconductor device and a method for producing the same by which the reliability of the device is improved, wherein a glass substrate 56 is adhered onto the surface of a silicon wafer 51 formed with a pad electrode 53, next, a via hole 81 extending from the rear surface of the silicon wafer to the pad electrode 53 is formed, in the meantime, a trench 82 extending along the dicing line center Ds and passing through the silicon wafer 51 from the rear surface of the silicon wafer 51 is formed, then, a buffer layer 61, a wiring layer 63, a solder mesh 65 and a solder ball 66 are formed on the rear surface of the silicon wafer 51 by the steps including the step of heat treatment following At last, the silicon wafer 51 supported by glass substrate 56 is diced through dicing into respective silicon chips 51a

Semiconductor device and method for producing the same

This invention provides a semiconductor device which assures an accurate electric and medicinal connections between electrodes by connecting the plurality of semiconductor chips having electrodes with a low melting point metallic member Bump electrodes are formed on a surface of a first semiconductor chip (1) Through holes (11) are formed in a second semiconductor chip (10) Through electrodes (12) having a clearance (13) in a central part of the through hole (11) are formed A low melting point metallic member (4) is interposed between connection surfaces of the bump electrodes (3) and the through electrodes (12) A part of the low melting point metallic member, when melted is allowed to flow into the clearance (13) By this arrangement a short circuit between the bump electrodes (3, 3) caused by providing an excess amount of the low melting point member (4) in the space between adjacent bump electrodes (3) can be prevented

Semiconductor device and method for making same

Method of processing objects comprising a surface portion made of an insulator

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