In this paper, failure mechanism of DT 4H-SiC power MOSFET under UIS measurement is evaluated by combination of experiment and theoretical research. Results has shown that: different from planar 4H-SiC power MOSFET, the gate oxide at the corner of of gate trench will be destroyed under UIS measurement, therefore, Device Under Test(DUT) failed. And then, measurement on the gate leakage and resistance between gate and source(Rgs) we have found that gate leakage increased sharply and Rgs only was 25Ω, however, the threshold voltage of failure device maintained unchanged. Also, theoretical analysis using TCAD on the inner electrical field under avalanche state have found that the maxium electrical field exist at the corner of gate trench which was consistent with the experimental result, and the maximum junction temperature did not over the melt point of metal.

Failure Mechanism of Double-Trench (DT) 4H-SiC Power MOSFET under UIS Measurement

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Failure Mechanism of Double-Trench (DT) 4H-SiC Power MOSFET under UIS Measurement