A method and apparatus for selectively etching doped semiconductor oxides faster than undoped oxides. The method comprises applying dissociative energy to a mixture of nitrogen trifluoride and hydrogen gas remotely, flowing the activated gas toward a processing chamber to allow time for charged species to be extinguished, and applying the activated gas to the substrate. Reducing the ratio of hydrogen to nitrogen trifluoride increases etch selectivity. A similar process may be used to smooth surface defects in a silicon surface.

Nf3/h2 remote plasma process with high etch selectivity of psg/bpsg over thermal oxide and low density surface defects

A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

Semiconductor chip having both compact memory and high performance logic

A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.

Semiconductor structure and manufacturing method thereof

A semiconductor device and method for forming the same for improving charge mobility in NMOS and PMOS devices simultaneously, the method including forming a first dielectric layer including a stress type selected from the group consisting of tensile stress and compressive stress over the respective PMOS and NMOS device regions; removing a portion of the first dielectric layer overlying one of the PMOS and NMOS device regions; forming a second dielectric layer including a stress type opposite from the first dielectric layer stress type over the respective PMOS and NMOS device regions; and, removing a portion of the second dielectric layer overlying one of the PMOS and NMOS device regions having an underlying first dielectric layer to form a compressive stress dielectric layer over the PMOS device region and a tensile stress dielectric layer over the NMOS device region

Local stress control for CMOS performance enhancement

A method is provided for forming a self aligned contact by etching an opening through a low doped or undoped dielectric layer such as phosphosilicate glass. The dielectric layer may be formed on a semiconductor layer which may include regions of monocrystalline silicon and undoped silicon dioxide. A first portion of a dielectric layer may be etched with a first etch chemistry, and a second portion of the dielectric layer may be etched with a second etch chemistry. The first etch chemistry may be substantially different than the second etch chemistry. In this manner, the first etch chemistry may have a substantially different etch selectivity than the second etch chemistry. For example, in an embodiment, the first etch chemistry may be selective to silicon nitride, and the second etch chemistry may be selective to undoped silicon oxide. Therefore, by using multiple etch chemistries to etch a single dielectric layer, a self aligned contact having optimized properties such as sidewall angle, aspect ratio, and critical dimension may be formed while an etch stop liner layer such as a silicon nitride layer may be eliminated.

Method of forming self aligned contacts

A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer ( 14 ) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures ( 46, 52, 54 ) are disposed. A silicon nitride layer ( 30 ) is in place below the BPSG layer ( 14 ), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer ( 14 ) during high temperature processes such as reflow and densification of the BPSG layer ( 14 ) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer ( 14 ) and the silicon nitride layer ( 30 ) using a two-step etch process. The first etch selectively etches silicon dioxide relative to silicon nitride, and thus stops on silicon nitride layer ( 30 ); besides serving as an etch stop, silicon nitride layer ( 30 ) protects underlying active regions ( 6, 7 ) from damage that may be caused by ionized oxygen released during oxide etch. A brief nitride etch is then used to clear silicon nitride layer ( 30 ), without damaging comer locations (NC) of the sidewall structures ( 11 ).

Silicon nitride dopant diffusion barrier in integrated circuits

An integrated circuit includes a conductive structure (66) is formed with a top layer of silicon nitride (62) and silicon nitride (70) sidewalls on a semiconductor substrate. The layer of silicon nitride (70) covering the sidewalls of the conductive structure (66) intersect with the layer of silicon nitride on top of the conductive structure with a relatively square shoulder. A subsequently deposited conductor makes contact with the surface of the semiconductor substrate (56) without shorting to the conductive structure (66) on the semiconductor substrate.

Silicon nitride sidewall and top surface layer separating conductors

An interconnect for a semiconductor device, comprising: a
first region 304 over a substrate 300, said first region having
a first resistivity; a second region 306 over said first region,
said second region having a lower resistivity than said first
region; and a third region 308 over said second region, said
third region having a higher resistivity than said second
region. The first region is preferably a layer of polysilicon
deposited over a gate oxide layer 302. The second region is a
silicide, such as tungsten disilicide, and the third region is
preferably polysilicon.

Interconnect structure comprising semiconductor material

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Papers

Silicon nitride dopant diffusion barrier in integrated circuits

Silicon nitride sidewall and top surface layer separating conductors

Interconnect structure comprising semiconductor material