The performance of some emerging nanotechnologies benefits from wave pipelining. The design of such circuits requires new models and algorithms. Thus we show how Majority-Inverter Graphs (MIG) can be used for this purpose and we extend the related optimization algorithms. The resulting designs have increased throughput, something that has traditionally been a weak point for the majority of non-charge-based technologies. We benchmark the algorithm on MIG netlists with three different technologies, Spin Wave Devices (SWD), Quantum-dot Cellular Automata (QCA), and NanoMagnetic Logic (NML). We find that the wave pipelined version of the netlists have an improvement in throughput over power of 23×, 13×, and 5× for SWD, QCA, and NML, respectively. In terms of throughput over area ratio, the improvement is 5×, 8×, and 3×, respectively.

/pdf/wave-pipelining-for-majority-based-beyond-cmos-technologies-2xc1tdpc1y.pdf

Wave pipelining for majority-based beyond-CMOS technologies

The development of high-yielding crops with drought tolerance is necessary to increase food, feed, fiber and fuel production. Methods that create similar environmental conditions for a large number of genotypes are essential to investigate plant responses to drought in gene discovery studies. Modern facilities that control water availability for each plant remain cost-prohibited to some sections of the research community. We present an alternative cost-effective automated irrigation system scalable for a high-throughput and controlled dry-down treatment of plants. This system was tested in sorghum using two experiments. First, four genotypes were subjected to ten days of dry-down to achieve three final Volumetric Water Content (VWC) levels: drought (0.10 and 0.20 m3 m-3) and control (0.30 m3 m-3). The final average VWC was 0.11, 0.22, and 0.31 m3 m-3, respectively, and significant differences in biomass accumulation were observed between control and drought treatments. Second, 42 diverse sorghum genotypes were subjected to a seven-day dry-down treatment for a final drought stress of 0.15 m3 m-3 VWC. The final average VWC was 0.17 m3 m-3, and plants presented significant differences in photosynthetic rate during the drought period. These results demonstrate that cost-effective automation systems can successfully control substrate water content for each plant, to accurately compare their phenotypic responses to drought, and be scaled up for high-throughput phenotyping studies.

https://lib.dr.iastate.edu/cgi/viewcontent.cgi?article=1622&context=agron_pubs

A cost-effective and customizable automated irrigation system for precise high-throughput phenotyping in drought stress studies.

Electronic Design Automation (EDA) is essential for the design of large-scale microelectronic systems. In this article, EDA methodologies, techniques, and algorithms used to develop superconductive computing systems are reviewed. The semicustom standard cell-based design flow, common in conventional CMOS circuits, is widely adopted in modern superconductive digital circuits. Differences and issues in CAD flows as compared to CMOS design methodologies are highlighted. The most common stages of these design flows, from high-level simulation to physical layout, are described. These stages are grouped into three areas: simulation/modeling, synthesis/place and route, and verification. Modern approaches and tools for superconductive circuits are reviewed for each of these areas.

Design Automation of Superconductive Digital Circuits: A review

of the Dissertation Energy-Efficient Wide Datapath Integer Arithmetic Logic Units Using Superconductor Logic by Christopher Lawrence Ayala Doctor of Philosophy in Computer Engineering Stony Brook University 2012 Complementary Metal-Oxide-Semiconductor (CMOS) technology is currently the most widely used integrated circuit technology today. As CMOS approaches the physical limitations of scaling, it is unclear whether or not it can provide long-term support for niche areas such as high-performance computing and telecommunication infrastructure, particularly with the emergence of cloud computing. Alternatively, superconductor technologies based on Josephson junction (JJ) switching elements such as Rapid Single Flux Quantum (RSFQ) logic and especially its new variant, Energy-Efficient Rapid Single Flux Quantum (ERSFQ) logic have the capability to provide an ultra-high-speed, low power platform for digital systems. The objective of this research is to design and evaluate energyefficient, high-speed 32-bit integer Arithmetic Logic Units (ALUs)

Energy-Efficient Wide Datapath Integer Arithmetic Logic Units Using Superconductor Logic

In 3G mobile terminals the Viterbi Decoder consumes approximately one third of the power consumption of a base band mobile transceiver. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. A low power Viterbi decoder is designed in circuit level using self reset logic and wave pipelining technique is implemented for high speed operation. The Viterbi decoder consists of four units like branch metric unit, add compare and select unit and the survivor path memory unit. All these units are designed using the self reset logic and wave pipelining, and simulated with its layout using MICROWIND TOOL in the 0.65nm technology, 1.8V Vdd and at a frequency of 10GHz. The simulation result shows that the power consumption is reduced by 70.55% and the speed of the circuit is increased by 45.83% compared to the Single Rail Domino Logic for constraint length of K =3 to 7.

/pdf/wave-pipelined-vlsi-architecture-for-a-viterbi-decoder-using-2lgh8z9ust.pdf

Wave Pipelined VLSI Architecture for a Viterbi Decoder Using Self Reset Logic with 0.65nm Technology

This study presents a novel design approach combining wave pipelining and self reset logic, which provides an elegant solution at high-speed data throughput with significant savings in power and area as compared with other dynamic CMOS logic implementations. To overcome some limitations in SRL art, we employ a new SRL family, namely, dual-rail self reset logic with input disable (DRSRL-ID). These gates depict fairly constant timing parameters, specially the width of the output pulse, for varying fan-out and logic depth, helping accommodate process, supply voltage, and temperature variations (PVT). These properties simplify the implementation of wave pipelined circuits. General timing analysis is provided and compared with previous implementations. Results of circuit implementation are presented together with conclusions and future work.

/pdf/wave-pipelining-using-self-reset-logic-584y54n40z.pdf

Wave pipelining using self reset logic

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Wave pipelining using self reset logic