In this invention, the instrumentation circuit or instrumentation code is added to the original design by the verification software, which is executed in a computer. The simulation consists of a front-end simulation and a back-end simulation. The front-end simulation can use an equivalent model at different abstraction level, or a simulation model for the back-end simulation. The back-end simulation uses the simulation result of front-end simulation so that it can run one or more simulation runs sequentially or in parallel. Or models at lower level of abstraction are simulated together with a model at higher level of abstraction in parallel using two or more simulators. Also, the debugging method with high visibility and controllability for the verification using a physical prototype in the in-circuit or in-system environment is provided by simulation using a simulator or a virtual prototype, and the dynamic information collected from a physical prototype in real time.

Dynamic-based verification apparatus for verification from electronic system level to gate level, and verification method using the same

An analysis system may perform network analysis on data gathered from an executing application. The analysis system may identify relationships between code elements and use tracer data to quantify and classify various code elements. In some cases, the analysis system may operate with only data gathered while tracing an application, while other cases may combine static analysis data with tracing data. The network analysis may identify groups of related code elements through cluster analysis, as well as identify bottlenecks from one to many and many to one relationships. The analysis system may generate visualizations showing the interconnections or relationships within the executing code, along with highlighted elements that may be limiting performance.

Increasing Performance at Runtime from Trace Data

A system, method of automated testing and control of networked devices is provided. One or more test cases are defined in a test plan for execution against a plurality of networked devices. The test cases are created using a command defined grammar comprising verbs which characterize how commands or actions should be performed. Abstraction markers allow for device-specific characteristics to be mapped to a target device, without modification of the test cases and the test plan itself. The verbs and abstraction markers, once mapped to a target device form device-specific commands comprising actions and device-specific characteristics which are executed against the target networked device. The resulting responses are parsed against expected responses and a result or verdict is assigned. By providing command grammar and abstraction capability a common test plan and test cases can be applied across a range of diverse networked devices without require user intervention or modification.

Automated testing and control of networked devices

Periodicity similarity between two different tracer objectives may be used to identify additional input parameters to sample. The tracer objectives may be individual portions of a large tracer operation, and each of the tracer objectives may have separate set of input objects for which data may be collected. After collecting data for a tracer objective, other tracer objectives with similar periodicities may be identified. The input objects from the other tracer objectives may be added to a tracer objective and the tracer objective may be executed to determine a statistical significance of the newly added objective. An iterative process may traverse multiple input objects until exhausting possible input objects and a statistically significant set of input objects are identified.

Periodicity optimization in an automated tracing system

As processes shrink, gate delay improves much faster than the delay in long wires. Therefore, the long wires increasingly determine the maximum clock rate, and hence performance, of more and more chips. One solution to this problem is to pipeline the global interconnect, enabling the whole chip to run at the speed of local operations. While known to work well, this optimization is seldom used because of practical difficulties - it is hard to change the RTL, test vectors become invalid, and it's hard to prove correctness of any changes. Here we look at some ways these difficulties could be overcome.

Methodologies and tools for pipelined on-chip interconnect

A system and method of verifying an electronic system. A verification kernel is provided and the electronic system is expressed as a logic design. A wrapper is defined, wherein the wrapper is an interface between the logic design and the verification kernel. Tests to be run against the logic design are placed within a diagnostic program and an interface between the diagnostic program and the verification kernel is defined. The tests are then executed against the logic design. The results of the tests are captured and validated against expected results.

Abstract verification environment

The complexity of large-scale multiprocessors has burdened the design and verification process making complexity-effective functional verification an elusive goal. We propose a solution to the verification of complex systems by introducing an abstracted verification environment called Raven. We show how Raven uses standard C/C++ to extend the capability of contemporary discrete-event logic simulators. We introduce new data types and a diagnostic programming interface (DPI) that provide the basis for Raven. Finally, we show results from an interconnect router ASIC used in a large-scale multiprocessor.

/pdf/verifying-large-scale-multiprocessors-using-an-abstract-12l4r25nd2.pdf

Verifying large-scale multiprocessors using an abstract verification environment

A single node of a modern scalable multiprocessor consists of several ASICs comprising tens of millions of gates. This level of integration and complexity imposes an enormous onus on the verification process. A variety of tools, ranging from discrete-event logic simulation to formal model checking, can be used to attack this problem. Unfortunately, conventional simulation techniques, with their primitive interface to the hardware (i.e. test vectors), are inadequate tools for reasoning about the correctness of complex architectural features, such as cache coherence protocols and memory consistency models. Similarly, model checkers offer very limited utility on such large designs. We have previously proposed a novel verification framework, called Raven, that addresses many of these challenges. In this paper we examine the performance implications of verifying systems at higher levels of abstraction. A detailed performance analysis is conducted to compare this higher-level approach against an equivalent Verilog test bench. We establish lower and upper bounds on the performance of the Raven environment executing on a single-processor on a set of distributed processors, and on a shared-memory multiprocessor.

A balanced approach to high-level verification: performance trade-offs in verifying large-scale multiprocessors

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Abstract verification environment

Verifying large-scale multiprocessors using an abstract verification environment

A balanced approach to high-level verification: performance trade-offs in verifying large-scale multiprocessors