Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~1011 neuron based) large neural networks.

/pdf/leaky-integrate-and-fire-neuron-by-charge-discharge-dynamics-1zlow0lmpg.pdf

Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET.

The human brain comprises about a hundred billion neurons connected through quadrillion synapses. Spiking neural networks (SNNs) take inspiration from the brain to model complex cognitive and learning tasks. Neuromorphic engineering implements SNNs in hardware, aspiring to mimic the brain at scale (i.e., 100 billion neurons) with biological area and energy efficiency. The design of ultra-energy-efficient and compact neurons is essential for the large-scale implementation of SNNs in hardware. In this article, we have experimentally demonstrated a partially depleted (PD) silicon-on-insulator (SOI) MOSFET-based leaky integrate-and-fire (LIF) neuron, where energy efficiency and area efficiency are enabled by two elements of the design–first is the tunneling-based operation and the second is a compact subthreshold SOI control circuit design. Band-to-band tunneling (BTBT)-induced hole storage in the body is used for the “integrate” function of the neuron. A compact control circuit “fires” a spike when the body’s potential exceeds the firing threshold. The neuron then “resets” by removing the stored holes from the body contact of the device. Additionally, the control circuit provides “leakiness” in the neuron, which is an essential property of the biological neurons. The proposed neuron provides $10\times $ higher area efficiency compared to the CMOS design with equivalent energy/spike. Alternatively, it has a $10^{4}\times $ higher energy efficiency at area-equivalent neuron technologies. Biologically comparable energy efficiency and area efficiency, along with CMOS compatibility, make the proposed device attractive for large-scale hardware implementation of SNNs.

pdf/band-to-band-tunneling-based-ultra-energy-efficient-silicon-46r1hv7d5x.pdf

Band-to-Band Tunneling Based Ultra-Energy-Efficient Silicon Neuron

Electron-beam inspection (eBI) of the contact (CA) module for silicon-on-insulator (SOI) technology is discussed in this paper. Voltage contrast is used to detect CA opens in the SRAM and both CA opens and shorts in special test structures. The inspection is performed after the tungsten chemical mechanical planarization (W CMP) step. In-line transmission electron microscope (TEM) samples at select defect sites are then prepared and imaged to determine the failure mechanism. This methodology greatly enhances yield learning and provides quick feedback for lithography and etch process adjustments.

Characterization of contact module failure mechanisms for SOI technology using E-beam inspection and in-line TEM

We present a substantially enhanced HSPICE feature that extra cts MOSFET threshold voltage (VT) based on the constant-current definition universally adopted by fabs to measure, specify, and monitor VT. With simulated VT now conveniently correlated to measurement, this capability enables faster design of robust analog circuits in cutting-edge CMOS technologies where voltage margins are critically limited and only predictive models, subjec t to periodic retargeting, are available during design. The feature was developed and evaluated usin g a 32-nm technology model and subsequently introduced in the 2009.09 HSPICE release. Operating poi nt, DC, AC, and most importantly transient analyses are supported for industry-s tandard BSIM4, BSIMSOI4, and PSP MOSFET models.

/pdf/constant-current-threshold-voltage-extraction-in-hspice-for-2u3lyw4vka.pdf

Constant-Current Threshold Voltage Extraction in HSPICE for Nanoscale CMOS Analog Design

As processors emerge with multiple wireline interfaces for high-performance digital media, a common multi-protocol clock system is essential for cost and power reduction. We present a 45nm SOI-CMOS system that clocks an 8-lane processor I/O designed for PCI Express®, DisplayPort, and TMDS. Its ring-VCO PLL (RO-PLL) achieves 0.99ps rms jitter that can be reduced further to 0.55ps upon switching to its auxiliary LC-VCO PLL (LC-PLL). As seen in Fig. 13.2.1, the clock system contains the two independent frequency synthesizers, an arrangement of programmable dividers to provide the required frequencies, and clock distribution circuitry. Furthermore, design-for-test features are embedded to correct for PVT variation for optimum jitter performance and to monitor PLL bandwidth and jitter peaking.

/pdf/a-45nm-soi-cmos-dual-pll-processor-clock-system-for-multi-soz1532gnd.pdf

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O

In this paper we present, an overview of partial depleted Silicon on Insulator (PD SOI) CMOS transistor technologies for high performance microprocessors. To achieve a “high performance per watt” figure of merit, transistor technology elements like PD SOI, strained Si, aggressive junction scaling, asymmetric devices need hand-in-hand development with multiple core- and power efficient designs. These techniques have been developed, applied and optimized for 65/45nm volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32nm design rules, High K Metal Gate (HKMG) technology is key. Different HKMG integrations as well as future strained Si technologies like strained silicon directly bonded on SOI and embedded Si:C are discussed.

Advanced SOI CMOS transistor technology for high performance microprocessors

In this paper we present an overview of partially depleted Silicon on Insulator (PD SOI) CMOS transistor technologies for high performance microprocessors. To achieve a “high performance per watt” figure of merit, transistor technology elements like PD SOI, strained Si, aggressive junction scaling, asymmetric devices need hand-in-hand development with multiple core- and power-efficient designs. These techniques have been developed, applied and optimized for 45 nm SOI volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32 nm design rules, High K Metal Gate (HKMG) technology is the key. Different HKMG integrations as well as future strained Si technologies, like strained silicon directly bonded on SOI, and embedded Si:C are discussed.

By locally adapting the blocking capability of gate insulation layers for N-channel transistors and P-channel transistors, the reliability and threshold stability of the P-channel transistor may be enhanced, while nevertheless electron mobility of the N-channel transistor may be kept at a high level. This may be accomplished by incorporating a different amount of a dielectric dopant into respective gate insulation layer portions.

Semiconductor device having a gate dielectric of different blocking characteristics

We present an overview of partially-depleted silicon-on-insulator (PD-SOI) CMOS transistor technologies for high-performance microprocessors. To achieve a “high performance per watt” figure of merit, transistor technology elements like PD-SOI, strained Si, aggressive junction scaling, and asymmetric devices need hand-in-hand development with multiple-core and power-efficient designs. These techniques have been developed, applied, and optimized for 45nm SOI volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32nm design rules, high-K metal-gate (HKMG) technology is key. Gate-first and replacement-gate HKMG integration as well as future strained Si technologies like strained silicon directly bonded on SOI and embedded Si:C are discussed.

Advanced SOI CMOS transistor technologies for high-performance microprocessor applications

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Advanced SOI CMOS transistor technology for high performance microprocessors

Advanced SOI CMOS transistor technology for high performance microprocessors

Semiconductor device having a gate dielectric of different blocking characteristics

Advanced SOI CMOS transistor technologies for high-performance microprocessor applications