Michael Parker
Cray
26 Papers
213 Citations
Michael Parker is an academic researcher from Cray. The author has contributed to research in topics: Distributed shared memory & Memory controller. The author has an hindex of 11, co-authored 26 publications. Previous affiliations of Michael Parker include University of Utah.
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Papers
Impulse: building a smarter memory controller
John B. Carter,Wilson C. Hsieh,Leigh Stoller,M. Swanson,Lixin Zhang,Erik Brunvand,Al Davis,Chen-Chi Kuo,R. Kuramkote,Michael Parker,Lambert Schaelicke,Terry Tateyama +11 more
- 09 Jan 1999
TL;DR: The design of the Impulse architecture is described, and how an Impulse memory system can be used to improve the performance of memory-bound programs is shown, which improves performance for the NAS conjugate gradient benchmark by 67%.
Interactive ray tracing for volume visualization
TL;DR: Presents a brute-force ray-tracing system for interactive volume visualization that is ideal for large data sets on current high-end parallel systems and several optimizations are used, including a volume bricking scheme and a shallow data hierarchy.
243
Interactive ray tracing for volume visualization
Steven G. Parker,Michael Parker,Yarden Livnat,Peter-Pike Sloan,Charles Hansen,Peter Shirley +5 more
- 31 Jul 2005
TL;DR: A brute-force ray tracing system for interactive volume visualization that is ideal for large datasets on current high-end parallel systems and several optimizations are used including a volume bricking scheme and a shallow data hierarchy.
91
Fast synchronization on shared-memory multiprocessors: An architectural approach
Zhen Fang,Lixin Zhang,John B. Carter,Liqun Cheng,Michael Parker +4 more
- 01 Oct 2005
TL;DR: An architectural innovation called active memory is presented that enables very fast atomic operations in a shared-memory multiprocessor and to the best of the authors' knowledge, synchronization based on active memory outforms all existing spinlock and non-hardwired barrier implementations by a large margin.
18
A low power architecture for embedded perception
Binu K. Mathew,Al Davis,Michael Parker +2 more
- 22 Sep 2004
TL;DR: This paper introduces a VLIW perception processor which uses a combination of clustered function units, compiler controlled dataflow and compiler controlled clock-gating in conjunction with a scratch-pad memory system to achieve high performance for perceptual algorithms at low energy consumption.