Several Elliptic Curve Processors (ECP) have been proposed in the literature associated with various architectures using different and sometimes confusing terminologies. This paper is a short review study of ECP architectures, considering the hardware platforms used for their implementations. The main design parameters of the ECP architectures, including the field choice and scalar multiplication algorithms were identified. Based on these parameters, a statistical study is conducted on a large collection of the published work. From the analysis of the collected data, several conclusions were deduced, such as the notion that binary field is easier to be implemented in hardware than prime field as well as the polynomial basis is dominant over other bases representation. Another significant conclusion is that Montgomery scalar multiplier has been used more than Lopez-Dahab, Binary, and NAF methods, particularly with the dominance of Lopez-dahab Projective coordinate.

Review of Elliptic Curve Processor architectures

This study presents an efficient and high-speed very large-scale integration implementation of point multiplication on binary Edwards curves over binary finite field GF(2
 m
) with Gaussian normal basis representation. The proposed implementation is a low-cost structure constructed by one digit-serial multiplier. In the proposed scheduling of point multiplication, the field multiplier is busy during point addition and point doubling computations. In the field multiplier structure, by using the logical effort technique the delay is optimally decreased and the drive ability of the circuit in the point multiplication architecture is increased. Also, to reduce area and number of transistors of the point multiplication circuit, all components are selected based on low-cost structures. The design is implemented in 0.18 μm CMOS technology over binary finite field GF(2
 233
). The results confirm the validity of the proposed structure and its high performance in terms of delay and area cost.

https://ietresearch.onlinelibrary.wiley.com/doi/epdf/10.1049/iet-cds.2017.0110

Full-custom hardware implementation of point multiplication on binary Edwards curves for application-specific integrated circuit elliptic curve cryptosystem applications

Asynchronous hardware implementations for crypto primitives

Balsa provides a design flow where asynchronous circuits are created from high-level specifications, but the syntaxdriven translation often results in performance overhead. To improve this, we exploit the fact that bundled-data circuits can be divided into data and control path. Hence, tailored optimisation techniques can be applied to both paths separately. For control path optimisation, STG-based resynthesis has been introduced (applying logic minimisation). However, solid results are missing so far due to problems with state explosion and the reliable insertion of reset logic. To tackle this, we use an adjusted STG decomposition algorithm and started to develop a new logic synthesizer (based on ideas of petrify) with proper reset insertion. Adding the adapted data path, we are now able to get first promising post synthesis simulation results using an industrial technology library (with a performance improvement of up to 23%). First experiments show additional potential for performance improvements (of up to 56%) when standard tools for synchronous design are applied to the data path.

Optimising Bundled-Data Balsa Circuits

Modern side-channel attacks (SCA) have the ability to reveal sensitive data from non-protected hardware implementations of cryptographic accelerators whether they be private or public-key systems. These protocols include but are not limited to symmetric, private-key encryption using AES-128, 192, 256, or public-key cryptosystems using elliptic curve cryptography (ECC). Traditionally, scalar point (SP) operations are compelled to be high-speed at any cost to reduce point multiplication latency. The majority of high-speed architectures of contemporary elliptic curve protocols rely on non-secure SP algorithms. This thesis delivers a novel design, analysis, and successful results from a custom differential power analysis attack on AES-128. The resulting SCA can break any 16-byte master key the sophisticated cipher uses and it’s direct applications towards public-key cryptosystems will become clear. Further, the architecture of a SCA resistant scalar point algorithm accompanied by an implementation of an optimized serial multiplier will be constructed. The optimized hardware design of the multiplier is highly modular and can use either NIST approved 233 & 283-bit Kobliz curves utilizing a polynomial basis. The proposed architecture will be implemented on Kintex-7 FPGA to later be integrated with the ARM Cortex-A9 processor on the Zynq-7000 AP SoC (XC7Z045) for seamless data transfer and analysis of the vulnerabilities SCAs can exploit.

/pdf/private-and-public-key-side-channel-threats-against-hardware-4bjp646b32.pdf

Private and Public-Key Side-Channel Threats Against Hardware Accelerated Cryptosystems

The current evolution of mobile devices and networked pervasive computer systems, such as wireless sensor networks, demand more and more functionality while consuming a minimum amount of energy. Security is one important need within such networked systems. With respect to this, the asynchronous design style is an accepted way of hardening crypto-cores against side-channel attacks. In this paper, we show a case study of designing a low-power asynchronous processor for elliptic-curve-cryptography. Therefore, we provide the theoretical base of this crypto-technique and a description about the applied designflow. For the evaluation, a layout has been created and compared with a synchronous implementation. The results show that even for a larger asynchronous implementation the power consumption is only one third of the synchronous one.

Design of a low-power asynchronous elliptic curve cryptography coprocessor

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Design of a low-power asynchronous elliptic curve cryptography coprocessor