Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT), the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM) devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

/pdf/review-on-physically-flexible-nonvolatile-memory-for-43wykav8d2.pdf

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

This paper describes newly developed delay and power monitoring schemes for minimizing power consumption by means of the dynamic control of supply voltage V DD and threshold voltage V TH in active and standby modes. In the active mode, on the basis of delay monitoring results, either V DD control or V TH control is selected to avoid any oscillation problem between them. In V DD control, on the basis of delay monitoring results, V DD is adjusted so as to be maintained at the minimum value at which the chip is able to operate for a given clock frequency. In V TH control, on the basis of power monitoring results, V TH is adjusted so as to maintain a certain switching current I SW /leakage current I LEAK ratio known to indicate minimum power consumption. In the standby mode, the precision of power monitoring (which detects optimum body bias by comparing subthreshold current I SUBTH to substrate current I SUB ) is improved by taking into consideration both the effects of lowering V DD and the effects of the presence of gate-oxide leakage current. Experimental results with a 90-nm CMOS device indicate that use of the proposed power monitoring results in the successful minimizing of power consumption. It does so by making it possible to: 1) maintain the I SW /I LEAK ratio in the active mode and 2) detect optimum body bias conditions (I SUBTH = I SUB ) within an error of less than 20% with respect to actual minimum leakage current values in the standby mode.

Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC–DC (SC DC–DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC–DC switches, DC–DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%–86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

/pdf/a-risc-v-vector-processor-with-simultaneous-switching-38llce1ae1.pdf

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI

An energy-harvesting wireless sensor node (WSN) integrates a 14-nm, 0.79-mm2, 32-b Intel Architecture core-based near-threshold voltage (NTV) microcontroller (MCU) that provides 17- $\mu \text{W}$ /MHz always-ON, always-sensing (AOAS) capability. The MCU implements four independent voltage-frequency islands, managed by an integrated power management unit and features a subthreshold voltage capable on-die oscillator and 42-nm fin-pitch, 8.3-pA leakage-per-bit SRAM. The MCU operates across a wide frequency (voltage) range from 297 MHz (1 V) to 0.5 MHz (308 mV), dissipating 23.5 mW to 21 $\mu \text{W}$ , and achieves $4.8\times $ better energy efficiency at an optimum supply voltage ( $V_{\text {OPT}}$ ) of 370 mV, 3.5 MHz, and 17 pJ/cycle. A functional AOAS WSN incorporating the NTV MCU shows promise for sustained $\mu \text{W}$ operation.

A Sub-cm 3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications

This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power systems that can operate in this region. However, exponential dependencies in subthreshold, require systems with either excessively large safety margins or that utilize adaptive techniques. Typically, these techniques include replica paths, sensors, or TED. Each of these methods adds system complexity, area, and energy overhead. As a run-time technique, TED is the only method that accounts for both local and global variations. The microprocessor presented in this paper utilizes adaptable error-detection sequential (EDS) circuits that can adjust to process and environmental variations. The results demonstrate the feasibility of the microprocessor, as well as energy savings up to 28%, when using the TED method in subthreshold. The microprocessor is an 8-bit core, which is compatible with a commercial microcontroller. The microprocessor is fabricated in 65 nm CMOS, uses as low as 4.35 pJ/instruction, occupies an area of 50,000 μm2, and operates down to 300 mV.

pdf/timing-error-detection-design-considerations-in-subthreshold-17vk3w94gb.pdf

Timing-Error Detection Design Considerations in Subthreshold: An 8-bit Microprocessor in 65 nm CMOS

This paper explores the effects of back-gate bias on switched-capacitor (SC) DC-DC converters in 28 nm UTBB FD-SOI. By using back-gate bias to optimize the control circuitry and switches, the SC converter can operate with a peak efficiency of 72% in sleep mode (100 nW load) and 83% in active mode (100 µW load).

Effects of back-gate bias on switched-capacitor DC-DC converters in UTBB FD-SOI

Significant demand for utlra-low power applications has provided an advantage for circuits capable of sub-threshold operation. The reduction of the supply voltage (V dd ) below the threshold voltage (V T ) of transistors, or sub-threshold, provides minimum energy consumption in digital CMOS logic. The exponential dependence of the drain current on V T variations leads to increased overdesign if sub-threshold circuits are to be robust. One solution to variability robustness is timing error detection (TED). Presented here is a TED latch capable of subthreshold operation. It was designed in 65 nm CMOS, has an operating voltage range of 0.2 V through 1.2 V, and a minimum energy point (MEP) of 0.4 V. At the MEP, the average power consumption for one clock period and an activity factor of α=0.5 is 0.37 nW. The area of the TED latch is 93 µm2.

/pdf/sub-threshold-operation-of-a-timing-error-detection-latch-52g5lyto3y.pdf

Sub-threshold operation of a timing error detection latch

Subthreshold source-coupled logic (STSCL) has been recently shown to be an advantageous logic style for ultra-low power applications. In the subthreshold region, STSCL provides improved power-delay performance and increased robustness over static CMOS logic. In this paper, we present a new timing error detection (TED) latch, or (TEDsc), which uses STSCL for detecting timing errors while using static CMOS logic for latching data. This allows for TEDsc to be easily integrated into a TED pipeline with static CMOS logic. At V dd =300 mV, TEDsc consumes 40% less power than an all-static CMOS subthreshold-capable TED latch.

A timing error detection latch using subthreshold source-coupled logic

Timing-error-detection (TED)-based systems have been shown to reduce power consumption or increase yield due to reduced margins. This paper shows that the increased adaptability can be a great advantage in the system design in addition to the well-known mitigated susceptibility to ambient and internal variations. Specifically, the design tolerances of the power management are relaxed to enable even greater system-level energy savings than what can be achieved in the logic alone. In addition, the system is simultaneously able to operate near the minimum error point. Here, the power management is a simplified dc–dc converter and the TED is based on time borrowing. The target application is a single-chip system on chip without external discrete components; thus, switched capacitors are used for the dc–dc. The system achieves 7.9% energy reduction at the minimum energy point simultaneously with a 36.4% energy–delay product decrease and a 15% increase in dc–dc efficiency. In addition, the effect of local variations on average system performance is reduced by 12%.

Implementing Minimum-Energy-Point Systems With Adaptive Logic

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