A method, system and apparatus for processing a radiographic image of a scanned object is disclosed. A pixel offset correction is performed in integer format on the radiographic image using saturation arithmetic to produce an image in integer format with any negative corrected values clipped to a value of zero. The resulting pixels are converted to floating point format and the converted pixels are multiplied by a gain factor. Optionally the resulting pixels are recursively averaged with previous results. The resulting pixels are converted to integer format and the converted pixel values are clamped to a maximum value using saturation arithmetic. Non-functional pixel correction is performed in integer format and the resulting pixel values are clamped to a maximum value using saturation arithmetic. An optional processing path replaces the recursive average by a linear average. The resulting pixel values are optionally filtered to enhance features of interest. The resulting pixel value is mapped in integer format to a palette index to establish an output pixel intensity having one of many intensity levels. The optional processing is controlled through the hardware interface of a real-time image controller as images are acquired.

Method, system and apparatus for processing radiographic images of scanned objects

A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of times that the loop is to be repeated. Alternatively, the repeat instruction may include an address of a register which holds the loop count value. The instruction immediately following the repeat instruction is the target instruction for repetition. The processing includes repeating execution of the target instruction according to the loop count value in a low processor cycle overhead manner. The processing may also include handling interrupts during repeat instruction processing in a low-overhead manner during the initial call of the interrupt service routine as well as upon returning from the interrupt service routine.

Repeat instruction with interrupt

A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PWM output signals have dual deadtime delay in which the delay between the inactivation of the first signal and the activation of the second signal may be different than the delay between the inactivation of the second signal and the activation of the first signal. This provides an improved capability to deal with non-symmetric switching characteristics of the external switching devices, and the circuitry to which they are connected. The dual deadtime pulse width modulation generator for a processor includes deadtime generation circuitry operable to generate a first pulse width modulated signal and a second pulse width modulated signal complementary to the first pulse width modulated signal, wherein there is a first delay between inactivation of the first pulse width modulated signal and activation of the second pulse width modulated signal, a second delay between inactivation of the second pulse width modulated signal and activation of the first pulse width modulated signal, and the first and second delays are not equal. The first delay and the second delay may be independently settable.

Processor with dual-deadtime pulse width modulation generator

According to the invention, a processing core that executes a parallel multiply accumulate operation is disclosed. Included in the processing core are a first, second and third input operand registers; a number of functional blocks; and, an output operand register. The first, second and third input operand registers respectively include a number of first input operands, a number of second input operands and a number of third input operands. Each of the number of functional blocks performs a multiply accumulate operation. The output operand register includes a number of output operands. Each of the number of output operands is related to one of the number of first input operands, one of the number of second input operands and one of the number of third input operands.

Methods and apparatus for performing parallel integer multiply accumulate operations

An apparatus and method are disclosed for multiple data pointer registers and a means for quickly switching active context between the data pointer registers.

Data pointers with fast context switching

A signed arithmetic data processing system (20) detects a multiply (MUL) or a multiply-and-accumulate (MAC) instruction in which a multiplier and a multiplicand each assume their respective maximum negative values. If one or both of the operands is not equal to its maximum negative value, the multiplication proceeds normally, such as in a modified Booth's multiplier/MAC (33). However, if both operands are equal to their respective maximum negative values, the data processing system (20) substitutes a maximum positive constant for the output of the multiplier/MAC (33). This substitution allows the result to be expressed with one fewer bits. The resulting error is very small and becomes insignificant in most digital signal processing algorithms, especially those based on fractional, saturation arithmetic. Alternatively, an extra bit of precision may be achieved for a given hardware size.

Method and apparatus for multiplying two numbers using signed arithmetic

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Method and apparatus for multiplying two numbers using signed arithmetic