Mark Chen
TSMC
22 Papers
101 Citations
Mark Chen is an academic researcher from TSMC. The author has contributed to research in topics: CMOS & Phase-locked loop. The author has an hindex of 6, co-authored 22 publications.
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Papers
In 0.53 Ga 0.47 As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate
Mao-Lin Huang,S. W. Chang,Mark Chen,C. H. Fan,Horng-Chih Lin,Chun-Hsiung Lin,R. L. Chu,K. Y. Lee,M. A. Khaderbad,Z. C. Chen,C.H. Chen,L. T. Lin,Hua-Tai Lin,Huicheng Chang,Chang-Ta Yang,Ying-Keung Leung,Yee-Chia Yeo,S.M. Jang,H. Y. Hwang,Carlos H. Diaz +19 more
- 16 Jun 2015
TL;DR: In this article, the epitaxial In 0.53 Ga 0.47 As channel MOSFETs were fabricated on 300 mm Si substrate and the channel layer exhibits high Hall electron mobility comparable to those grown on lattice matched InP substrates.
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19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications
Chao-Chieh Li,Min-Shueh Yuan,Chih-Hsien Chang,Yu-Tso Lin,Chia-Chun Liao,Kenny Hsieh,Mark Chen,Robert Bogdan Staszewski +7 more
- 01 Feb 2017
TL;DR: Energy harvesting (EH) is a topic of intensive research promising battery-free operation of massive networks of wireless IoT devices, but to simultaneously satisfy the EH and IoT, ultra-low-power (ULP) consumption with ultra- low-voltage supply are required.
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High performance In 0.53 Ga 0.47 As FinFETs fabricated on 300 mm Si substrate
Mao-Lin Huang,S. W. Chang,Mark Chen,Y. Oniki,Chen Hsin-Ping,Chun-Hsiung Lin,Wen-Chin Lee,M. A. Khaderbad,K. Y. Lee,Z. C. Chen,P. Y. Tsai,L. T. Lin,Ming-Huan Tsai,C. L. Hung,Tsung-Yi Huang,Yi-Hsiung Lin,Yee-Chia Yeo,S.M. Jang,H. Y. Hwang,Howard Wang,Carlos H. Diaz +20 more
- 14 Jun 2016
TL;DR: In this article, the extrinsic field effect mobility of In 0.53 Ga 0.47 As FinFETs is demonstrated. But, the performance is not as good as that of InP-based InP substrate.
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18.7 A 0.7V, 2.35% 3σ-Accuracy Bandgap Reference in 12nm CMOS
Chen Yi-Wen,Jaw-Juinn Horng,Chang Chin-Ho,Amit Kundu,Yung-Chow Peng,Mark Chen +5 more
- 01 Feb 2019
TL;DR: Bandgap reference (BGR) circuits are widely used due to their stable output voltage over process, supply voltage and temperature variations, but BGR for analog circuits is one of the bottlenecks for sub-1V supply operation because BGR supply voltage is limited by VEB+VDS.
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An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs
Feng Wei Kuo,Masoud Babaie,Huan-Neng Ron Chen,Lan-Chou Cho,Chewn-Pu Jou,Mark Chen,Robert Bogdan Staszewski +6 more
TL;DR: A time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS, based on a 1/8-length time-to-digital converter of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors.