Today's electronics scenario finds itself with the advancement in the field of foremost important component MOSFET. Though one-step ahead of MOSFET, power MOS transistor such as VDMOS has recently begun to rival bipolar devices in power handling capability. In this paper, the results of simulation of VDMOS transistor have been presented. Additionally, the transfer characteristics of the VDMOS transistor are simulated. The drain current (Ids) as a function of the gate voltage and of the drain voltage was simulated for different work function values as well as for several oxide thickness and gate lengths, respectively. The results obtained show that when the work function and the oxide thickness as well as the gate length increase, the threshold voltage also increases. The VDMOS transistor is virtually fabricated using ATHENA software and simulation is done with help of ATLAS software and all graphs are plotted using Tonyplot in Silvaco.

/pdf/i-v-characteristic-of-vertical-double-diffused-metal-oxide-1vhi7gg5.pdf

I_V Characteristic of Vertical Double Diffused Metal Oxide Semiconductor (VDMOS) Power Transistor Using Silvaco-TCAD

This work analyzed the interactions between gate oxide thickness (Tox), voltage dependence, and electron mobility (E-mobility) in the inversion layer, which controls the electron movement properties of 4H-SiC/SiO2. This paper also presents a calculation of gate oxide thickness in correlation with gate voltage mainly for high-voltage applications. The results of this work revealed that at low resistance, E-mobility increases with gate voltage and oxide thickness, which saturates at the point of value. Coulomb scattering and surface phonons at the inversion region of SiC MOSFETs are regarded as the two primary factors that limit E-mobility in these devices. In addition, the high interface trap density (Dit) causes a decrease in E-mobility. The findings from this study confirmed that the computed values of oxide thickness and simulation-based oxide thickness with regulated gate voltages have the least variation below 1%, asserting experimental and theoretical outcomes about the role of oxide thickness and electron movement at the 4H-SiC/SiO2 interfaces. These results indicate that understanding the E-mobility effect on oxide thickness in the SiC MOSFET inversion layer according to gate voltage is important, particularly in achieving an optimal 4H-SiC/SiO2 interface for high-power applications. 

Wide Bandgap SiC-Based Oxide Thickness Optimization by Computation and Simulation using Enhanced Electron Mobility with Regulated Gate Voltage Technique for High-Power 4H-SiC MOSFET

Modelling and Simulation of Design Variants for the Development of 4H-SiC Thyristors

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Modelling and Simulation of Design Variants for the Development of 4H-SiC Thyristors