Manish Kumar
Jaypee Institute of Information Technology
9 Papers
116 Citations
Manish Kumar is an academic researcher from Jaypee Institute of Information Technology. The author has contributed to research in topics: Eigenface & Facial recognition system. The author has an hindex of 5, co-authored 9 publications.
Chat about Author
Papers
Face recognition using principle component analysis, eigenface and neural network
Mayank Agarwal,Nikunj Jain,Manish Kumar,Himanshu Agrawal +3 more
- 07 Nov 2009
TL;DR: In this paper, the authors presented a methodology for face recognition based on information theory approach of coding and decoding the face image, the proposed methodology is connection of two stages - Feature extraction using principle component analysis and recognition using the feed forward back propagation Neural Network.
72
Low Power Techniques for Digital System Design
TL;DR: The authors have presented and analyzed some power reduction techniques that can be targeted at different levels of design hierarchy for different target platform and would also discuss concept of ACPI module designed for newer operating systems, which provides basic power management facilities to save system power.
26
More Precise FPGA Power Estimation and Validation Tool (FPEV_Tool) for Low Power Applications
TL;DR: An improvement over the existing power estimation model has been suggested termed as FPEV_Tool, accurately estimating the power of both types of digital circuits i.e. designs with clock enable and without clock enable with an average error of approximately 3% and peak error of 17%, respectively.
19
Analysis of Low Power Consumption Techniques on FPGA for Wireless Devices
TL;DR: An insight to minimize the power at architectural level of design hierarchy using XPower Analyzer as a CAD tool and the proposed techniques are applied on arithmetic and logical unit circuit for analysis purpose, as ALU is the heart of processing elements used in portable wireless devices.
15
Low Power Synthesis and Validation of an Embedded Multiplier for FPGA Based Wireless Communication Systems
TL;DR: The results suggested that the given low level power estimation models provide less accuracy (high % error) for the designs incorporated with low power reduction technique i.e. with ‘CE’.
8