Increases in on-chip communication delay and the large working sets of server and scientific workloads complicate the design of the on-chip last-level cache for multicore processors. The large working sets favor a shared cache design that maximizes the aggregate cache capacity and minimizes off-chip memory requests. At the same time, the growing on-chip communication delay favors core-private caches that replicate data to minimize delays on global wires. Recent hybrid proposals offer lower average latency than conventional designs, but they address the placement requirements of only a subset of the data accessed by the application, require complex lookup and coherence mechanisms that increase latency, or fail to scale to high core counts.In this work, we observe that the cache access patterns of a range of server and scientific workloads can be classified into distinct classes, where each class is amenable to different block placement policies. Based on this observation, we propose Reactive NUCA (R-NUCA), a distributed cache design which reacts to the class of each cache access and places blocks at the appropriate location in the cache. R-NUCA cooperates with the operating system to support intelligent placement, migration, and replication without the overhead of an explicit coherence mechanism for the on-chip last-level cache. In a range of server, scientific, and multiprogrammed workloads, R-NUCA matches the performance of the best cache design for each workload, improving performance by 14% on average over competing designs and by 32% at best, while achieving performance within 5% of an ideal cache design.

/pdf/reactive-nuca-near-optimal-block-placement-and-replication-wlxbgjp7xb.pdf

Reactive NUCA: near-optimal block placement and replication in distributed caches

htmlabstractWith the performance of modern computers improving at a rapid pace, database 
technology has problems with fully exploiting the benefits that each new hardware 
generation brings. This has caused a significant performance gap between 
general-purpose databases and specialized, application-optimized solutions for 
large-volume computation-intensive processing problems, as found in areas including 
information retrieval, scientific data management and decision support. 
This thesis attempts to enhance the state-of-the-art in architecture-conscious 
database research, both in the query execution layer as well as in the data storage 
layer, and in the way these work together. Thus, rather than focusing on 
an isolated problem or algorithm, the thesis presents a new database system 
architecture, realized in the MonetDB/X100 prototype, that combines a coherent 
set of new architecture-conscious techniques that are designed to work well 
together. 
The motivation for the new query execution layer comes from the analysis 
of the problems of two popular approaches to query processing: tuple-at-a-time 
operator pipelining, used in most existing systems, and column-at-a-time materializing 
operators, found in MonetDB. MonetDB/X100 proposes a new vectorized 
in-cache execution model, that exploits ideas from both approaches, and combines 
the scalability of the former with the high-performance bulk processing of 
the latter. This is achieved by modifying the traditional operator pipeline model 
to operate on cache-resident vectors of data using highly optimized primitive 
functions. Additionally, within this architecture, a set of hardware-conscious 
design and programming techniques is presented, enabling efficient execution 
of typical data processing tasks. The resulting query execution layer efficiently 
exploits modern super-scalar CPUs and cache-memory systems and achieves 
in-memory performance often one or two orders of magnitude higher than the 
existing approaches. 
In the storage area there are two hardware trends that significantly influence 
219 
220 Summary 
database performance. First, the imbalance between sequential disk bandwidth 
and random disk latency continuously increases. As a result, access methods that 
rely on random I/O become less attractive, making various forms of sequential 
access the preferred option. MonetDB/X100 follows this idea with ColumnBM 
– a bandwidth-optimized column store. Secondly, both disk bandwidth and latency 
improve significantly slower than the computing power of modern CPUs, 
especially with the advent of multi-core CPUs. ColumnBM introduces two techniques 
that address this issue. Lightweight in-cache compression allows trading 
some processor time for an increased perceived disk bandwidth. High decompression 
performance is achieved by applying the decompression on the RAMcache 
boundary, providing cache-resident data directly to the execution layer. 
Additionally, introduced family of compression methods provides performance 
an order of magnitude higher than previous solutions. Cooperative scans observe 
current system activity and dynamically schedule I/O operations to exploit overlapping 
demands of different queries. This allows to amortize the cost of disk 
access among multiple consumers, and also better utilize the available buffer 
space, providing much better performance with many concurrently executing 
queries. 
By combining the CPU-efficient processing with a bandwidth-optimized storage 
facility, MonetDB/X100 has been able to achieve its high in-memory raw 
query execution power also on huge disk-resident datasets. We evaluated its 
performance both on TPC-H decision support data sets as well as in the area 
of large-volume information retrieval (the Terabyte TREC task), where it successfully 
competed with the specialized solutions, both for in-memory and diskbased 
tasks.

/pdf/balancing-vectorized-query-execution-with-bandwidth-3bf5a3pf2b.pdf

Balancing vectorized query execution with bandwidth-optimized storage

Parallel Programming : for Multicore and Cluster Systems. 2. Edition

The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilization is becoming ever more important. Furthermore, available cores are expected to be underutilized due to the power wall and highly heterogeneous future workloads. This trend makes existing L2 cache management techniques less effective for two problems: increased capacity interference between working cores and longer L2 access latency. We propose a novel scalable cache management framework called CloudCache that creates dynamically expanding and shrinking L2 caches for working threads with fine-grained hardware monitoring and control. The key architectural components of CloudCache are L2 cache chaining, inter- and intra-bank cache partitioning, and a performance-optimized coherence protocol. Our extensive experimental evaluation demonstrates that CloudCache significantly improves performance of a wide range of workloads when all or a subset of cores are occupied.

/pdf/cloudcache-expanding-and-shrinking-private-caches-524lgo0upc.pdf

CloudCache: Expanding and shrinking private caches

Virtualization-assisted concurrent, autonomous self-test, or VAST, enables a multi-/many-core system to test itself, concurrently during normal operation, without any user-visible downtime. Such on-line self-test is required for large-scale robust systems with built-in support for circuit failure prediction, failure detection, diagnosis, and self-healing. The main idea behind VAST is hardware and software co-design of on-line self-test features in a multi-/many-core system through integration of: 1. multi-/many-core architecture, 2. virtualization software, and, 3. special self-test techniques such as BIST (built-in self-test) or CASP (concurrent autonomous chip self-test using stored patterns). As a result, optimized trade-offs in system design complexity, system performance and power impact, and test thoroughness are possible. Experimental results from an actual multi-core system demonstrate that: 1. VAST is practical and effective; and, 2. Special VAST-supported self-test policies enable extremely thorough on-line self-test with very small performance impact.

VAST: Virtualization-Assisted Concurrent Autonomous Self-Test

Integration Challenges and Tradeoffs for Terascale Architectures

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Integration Challenges and Tradeoffs for Terascale Architectures