This paper presents a novel architecture of on-chip clock generation employing a network of oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented prototype has 16 clocking domains operating synchronously in a frequency range of 1.1-2.4 GHz. The synchronization error between the neighboring clock domains is less than 60 ps. The fully digital architecture of the generation offers flexibility and efficient synchronization control suitable for use in synchronous SoCs.

/pdf/distributed-clock-generator-for-synchronous-soc-using-adpll-1e5uelm26p.pdf

Distributed clock generator for synchronous SoC using ADPLL network

In this paper we propose a F0 trajectories tracking method designed to work with monaural speech mixtures. A two speaker’s speech mixture is firstly preprocessed in order to extract some F0 candidates in each signal’s frame. A dynamic programming framework is then presented to generate each speaker’s F0 streams. The dynamic programming aims at selecting and clustering the F0 candidates given by the pre-processing

Ecole Doctorale « Sciences et Technologies de l'Information des Télécommunications et des Systèmes »

Les arbres classiques de distribution du signal d’horloge au sein des microprocesseurs synchrones presentent un certain nombre de limitations : skew, jitter, limitation de la frequence, influence de perturbations et de dispersions quelles que soient leurs natures. Ces facteurs, critiques pour les microprocesseurs modernes complexes, sont devenus la raison principale qui a pousse a la recherche d’autres types d’architecture de generation et de distribution du signal d’horloge. Un exemple d’un tel systeme alternatif est le reseau de PLLs couplees, ou les PLLs sont geographiquement distribuees sur la puce, et generent des signaux d’horloge locaux qui sont ensuite synchronises, en temps reel, par un echange d’information entre les PLLs voisines et une retroaction locale realise par leur correcteurs. La nature active du reseau de PLLs de generation et de distribution du signal d’horloge, qui peut permettre de surpasser les limitations mentionnees plus tot, oblige a sortir du cadre classique des outils et des methodes de la Microelectronique habituellement appliques a l’etude et a la conception de ce type de systemes. En effet, les aspects dynamiques de bouclage et de transformation de signaux au sein de tels systemes complexes rendent leur conception extremement difficile voire parfois impossible. La difficulte principale consiste en un changement des proprietes d’un sous-systeme local independant par rapport aux proprietes du meme sous-systeme faisant partie du reseau. Effectivement, il existe beaucoup de methodes et d’outils de conception d’une PLL isolee garantissant un comportement et des proprietes locales desires. Neanmoins, ces proprietes desirees locales, selon la topologie d’interconnexion consideree, ne sont pas forcement conservees quand il s’agit d’un reseau de PLLs interconnectees et de son comportement global. Le but principal de cette these est ainsi de developper une methode de synthese de la loi de commande decentralisee realisee au sein de chaque sous-systeme (tel qu’une PLL) assurant le comportement desire pour le reseau global. Une methode de transformation du probleme de synthese globale en un probleme equivalent de synthese d’une loi de commande locale est proposee en se basant sur l’hypothese des sous-systemes identiques interconnectes en reseau. Le lien entre les proprietes locales et globales est etabli grâce aux approches d’Automatique avancee telles que les approches entree-sortie et la dissipativite. Ce choix de methode permet non seulement de reduire considerablement la complexite du probleme initial mais aussi de ramener le probleme de synthese a une forme proche des methodes de conception locale utilisees en Microelectronique, ce qui garantit une continuite logique de leur evolution. Ensuite la methode proposee est combinee avec la commande H∞ et l’optimisation sous contraintes LMIs conduisant au developpement d’algorithmes efficaces de resolution du probleme pose. Elles sont a la fois particulierement bien adaptees a l’application consideree, c’est-a-dire a la synchronisation d’un reseau de PLLs, et sont facilement generalisables aux autres types de problemes de commande de systemes de grande dimension. Le premier aspect permet une integration naturelle et aisee de la methode dans le flux de conception existant en Microelectronique, tres riche et mature a ce jour, alors que le deuxieme offre une solution a d’autres problemes de commande de systemes interconnectes en reseau, un champ d’application aujourd’hui en plein essor.

Réseau de PLLs distribuées pour synthèse automatique d'horloge de MPSOCs synchrones

In this paper, we present an FPGA modelling of a distributed and synchronized clock generation for different clock domains based on coupled all-digital phase locked loops (ADPLLs). An implementation of a programmable and reconfigurable 10 ×10 ADPLL network is described, designed for prototyping distributed clock generation in large synchronous system on chip (SoC). The paper emphasizes the reconfigurability of proposed system, which allows exploiting stability issues and nonlinear behavior of a N × M network of coupled oscillators (the dimension can be configured from 1 × 1 to 10 × 10). Configurations with different parameters are compared and analyzed. A dynamic setup mechanism is proposed, allowing selecting the desired synchronized state. Experimental results validate theoretical analysis about circuit parameters and demonstrate the global synchronization of network and performance for different configurations.

/pdf/fpga-prototyping-of-large-reconfigurable-adpll-network-for-xngcj4t3mp.pdf

FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation

In this paper, we investigate a test strategy for characterization of clock error statistics between two clock domains in high-speed clocking systems (gigahertz and more). The method allows an indirect measurement (not based on time interval measurement) of clock error distribution by observing the integrity of a periodic sequence transmitted between two clocking domains. The method is compatible with fully on-chip implementation, and the readout of result to off-chip signals is cadenced at low rate. The strategy aims at picoseconds resolution without complex calibration. The idea was first validated by a discrete prototype at downscaled frequencies, and then a high frequency on-chip prototype was designed using 65 nm CMOS technology. Simulation results predict a measurement precision of less than ±2.5 ps. The article presents the theory, exposes the hardware implementation, and reports the experimental validation and simulation results of two prototypes.

/pdf/on-chip-clock-error-characterization-for-clock-distribution-3b1a5ck379.pdf

On-chip clock error characterization for clock distribution system

This paper presents an FPGA platform for the design and study of network of coupled All-Digital Phase Locked Loops (ADPLLs), destined for clock generation in large synchronous System on Chip (SoC). An implementation of a programmable and reconfigurable 4×4 ADPLL network is described. The paper emphasizes the difference between the FPGA and ASIC-based implementation of such a system, in particular, implementation of digitally controlled oscillators and phase-frequency detector. The FPGA-implemented network allows studying complex phenomena related to coupled ADPLL operation and exploiting stability issues and nonlinear behavior. A dynamic setup mechanism has been proposed for the network, allowing selecting the desirable synchronized state. Experimental results demonstrate the global synchronization of network and performance of the network for different configurations.

/pdf/fpga-implementation-of-reconfigurable-adpll-network-for-37veezvk68.pdf

FPGA implementation of reconfigurable ADPLL network for distributed clock generation

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FPGA implementation of reconfigurable ADPLL network for distributed clock generation