▪ Abstract The transition to copper-based interconnects for sub-quarter-micron device technologies has generated significant challenges in the identification and development of the robust material and process technologies required to form reliable multilevel metallization interconnects. In particular, a critical need exists for the identification and development of diffusion barrier/adhesion promoter liner materials that provide excellent performance in preventing the diffusion and intermixing of copper with the adjacent dielectric and semiconductor regions of the computer chip. This review summarizes key technology trends in interconnect metallization, with emphasis on ultrathin liner materials, predominant diffusion mechanisms in liner materials, and most promising candidate liners for copper metallization. Key results are presented from the development of physical vapor deposition and chemical vapor deposition processes for binary refractory metal nitrides, such as tantalum nitride and tungsten nitride...

Ultrathin Diffusion Barriers/Liners for Gigascale Copper Metallization

Development of better diffusion barriers for Cu metallization is one of the key issues for the microelectronics industry. Althoughmetallic diffusion barriers offer many advantages, their application is hindered due to their inferior thermal stability relative toceramic barriers. Here we report on a metallic diffusion barrier, NbSiTaTiZr, which shows thermal stability comparable to ceramicbarriers. The outstanding performance of NbSiTaTiZr is due to its better structural and chemical stability at high temperatures.©2011 The Electrochemical Society. [DOI: 10.1149/2.056111jes] All rights reserved.Manuscript submitted June 10, 2011; revised manuscript received August 15, 2011. Published October 5, 2011.

https://ir.nctu.edu.tw:443/bitstream/11536/14828/1/000295626000063.pdf

Thermal Stability and Performance of NbSiTaTiZr High-Entropy Alloy Barrier for Copper Metallization

Copper (Cu) migration into semiconductor materials like silicon is a well-known and troublesome phenomenon often causing adverse effect on devices. Generally a diffusion barrier layer is added to prevent Cu metallization. We demonstrate an organic nonvolatile memory device by controlling the Cu-ion (Cu+) concentration within the organic layer. When the Cu+ concentration is high enough, the device exhibits a high conductive state due to the metallization effect. When the Cu+ concentration is low, the device displays a low conductance state. These two states differ in their electrical conductivity by more than seven orders of magnitude and can be precisely switched by controlling the Cu+ concentration through the application of external biases. The retention time of both states can be more than several months, and the device is promising for flash memory application. Discussions about the device operation mechanism are provided.

/pdf/organic-nonvolatile-memory-by-controlling-the-dynamic-copper-3esmt3g5dv.pdf

Organic nonvolatile memory by controlling the dynamic copper-ion concentration within organic layer

Ta thin films were grown on Si(001) and polycrystalline Si substrates by plasma-enhanced atomic-layer deposition (PE-ALD) using TaCl5 and atomic hydrogen as precursors. The grown films have resistivity of 150–180 μm cm with a small Cl concentration between 0.5 and 2 at. %. The diffusion barrier properties were investigated using bilayer structures consisting of 200 nm Cu deposited by sputtering on ALD Ta films with various thicknesses. Three in situ analysis techniques consisting of x-ray diffraction, elastic light scattering, and resistance analysis were used to determine the diffusion barrier failure temperature of Ta films. The barriers were annealed at a temperature ramp rate of 3 °C/s from 100 to 1000 °C in forming gas. For this method using x-ray diffraction, the barrier failure temperatures were determined by monitoring the disappearance of the Cu(111) x-ray diffraction peak and appearance of Cu silicide diffraction peaks. At the diffusion barrier failure temperature, elastic light scattering indic...

Diffusion barrier properties of transition metal thin films grown by plasma-enhanced atomic-layer deposition

Preface (Kazuo Kondo) PART 1 Copper electrodepositon and additive chemistry Chapter 1 - Copper electrodeposition (Masayuki Yokoi) Chapter 2 - Suppression effect and Additive Chemistry (Masayuki Yokoi) Chapter 3- Acceleration effect (Dale P. Barkey) Chapter 4- Modeling and Simulation ( Yutaka Kaneko) PART 2 Copper on chip metallization Chapter 5- Frontiers of Cu Electrodeposition and Electroless Plating for On-Chip Interconnects (James R. Rohan) Chapter 6- Microstructure of Evolution of Copper in Nano-scale Interconnect Features (James Kelly, Christopher Parks, James Demarest, and Christopher Penny) Chapter 7- Direct Copper Plating (Aleksandar Radisic and Philippe M. Vereecken) Part 3 - Through Silicon Via and Other Methods Chapter 8- Through Silicon Via (Kazuo Kondo) Chapter 9- Build-up Printed Wiring board (Kiyoshi Takagi a and Toshkazu Okubo) Chapter 10- Copper Foil Smooth on Both Sides for Lithium Ion Battery (Akitoshi Suzuki and Jun Shinozaki) Chapter 11- Through hole plating (Wei-Ping Dow)

Copper electrodeposition for nanofabrication of electronics devices

Diffusion barrier properties of very thin sputtered Ta and reactively sputtered TaN films used as a barrier layer between Cu and Si substrates were investigated using electrical measurement and materials analysis. The Cu/Ta/p + -n junction diodes with the Ta barrier of 5, 10, and 25 nm thicknesses were able to sustain a 30 min thermal annealing at temperatures up to 450, 500, and 550°C, respectively, without causing degradation to the device's electrical characteristics. The barrier capability of Ta layer can be effectively improved by incorporation of nitrogen in the Ta film using reactive sputtering technique. For the Cu/TaN/p + -n junction diodes with the TaN barrier of 5, 10, and 25 nm thicknesses, thermal stability was able to reach 500, 600, and 700°C, respectively. We found that failure of the very thin Ta and TaN barriers was not related to Ta silicidation at the barrier/Si interface. Failure of the barrier layer is presumably due to Cu diffusion through the barrier layer during the process of thermal annealing via local defects, such as grain boundaries and stress-induced weak points.

https://ir.nctu.edu.tw:443/bitstream/11536/32541/1/000074474500055.pdf

Barrier Properties of Very Thin Ta and TaN Layers Against Copper Diffusion

This work studies the thermal stability of Cu/WSi x /p + -n and Cu/WSiN/WSi x /p + -n diodes in which the WSi x barrier layers were deposited by chemical vapor deposition to a thickness of about 50 nm using SiH 4 /WF 6 chemistry with the SiH 4 /WF 6 flow rates of 6/2 sccm, while the WSiN layers were formed by in situ N 2 plasma treatment on the chemically vapor deposited WSi x (CVD-WSi x ) surfaces. Without N 2 plasma treatment, the thermal stability of Cu/WSi x (50 nm)/p + -n junction diodes was found to reach 500°C; with N 2 plasma treatment, the resultant Cu/WSiN/WSi x (50 nm)/p + -n junction diodes were able to retain integrity of electrical characteristics up to at least 600°C. Failure mechanism of the WSiN/WSi x bilayer in the Cu/WSiN/WSi x /Si structure was closely related to the WSi x /Si interface reaction and the tungsten silicide formation of the WSi x layer. Thus, barrier capability of the WSiN/WSi x bilayer can be further improved by suppressing the WSi x /Si interface reaction and the silicidation of the WSi x layer. The thermal stability of Cu/barrier/p + -n diodes was further raised to 650°C by using a multilayer barrier structure of WSiN/WSi x (50 nm)/WSiN/WSi x (10 nm) or a WSiN/WSi y (y > 1) barrier. We conclude that the post-CVD-WSi x treatment with in situ N 2 plasma is a simple, practical, and efficient method of improving the WSi x -based barrier capability for Cu metallization.

https://ir.nctu.edu.tw:443/bitstream/11536/31427/1/000079811000057.pdf

Effective Improvement on Barrier Capability of Chemical Vapor Deposited WSi x Using N 2 Plasma Treatment

Thin-Film properties and barrier effectiveness against copper (Cu) diffusion of a thin amorphous WSi x layer were investigated. The amorphous WSi x layer was deposited by the chemical vapor deposition (CVD) method using the SiH 4 /WF 6 chemistry with the activation energy determined to be 3.0 kcal/mol. The CVD-WSi x film has a low film stress, low electrical resistivity, and excellent step coverage. The resistivity of the amorphous CVD-WSi x layer increases with the deposition temperature, but the residual stress of the layer decreases with the deposition temperature. The WSi x /Si structure is thermally stable up to at least 600°C, while the copper-contacted Cu/WSi x /Si structure with a 50 nm thick WSi x barrier is stable only up to 550°C. Moreover, the Cu/WSi x /p + -n junction diodes can sustain a 30 min thermal annealing up to 500°C without causing degradation in electrical characteristics. Barrier failure of the WSi x layer in the Cu/WSi x /Si structure at temperatures above 550°C is attributed to Cu atoms diffusion via fast paths in the WSi x layer. These fast paths were presumably developed from grain growth of the WSi x layer and/or thermal-stress-induced weak points in the WSi x layer.

https://ir.nctu.edu.tw:443/bitstream/11536/31724/1/000077171500028.pdf

Thin‐Film Properties and Barrier Effectiveness of Chemically Vapor Deposited Amorphous WSi x Film

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Barrier Properties of Very Thin Ta and TaN Layers Against Copper Diffusion

Effective Improvement on Barrier Capability of Chemical Vapor Deposited WSi x Using N 2 Plasma Treatment

Thin‐Film Properties and Barrier Effectiveness of Chemically Vapor Deposited Amorphous WSi x Film