Excessive power supply noise can affect path delay and cause overkill during delay test. This paper presents low-cost noise models for fast power supply noise analysis and timing analysis considering noise impact. Our prior work only considered array-bond chips. This work proposes a noise analysis methodology that can be applied to wire-bond chips as well as array-bond chips. Experiments were performed on an industrial design. Silicon results show as much as a 15% delay variation due to different don't care fill approaches. The power supply noise impact on delay must be taken into account when delay tests are applied.

/pdf/power-supply-noise-in-delay-testing-49prchpbib.pdf

Power Supply Noise in Delay Testing

Electrostatic discharge (ESD) is a critical reliability concern for microchips. This paper presents a comprehensive computer-aided design tool for ESD applications. Specifically, the authors develop an improved and robust MOS model and implement such a model into the industry standard Cadence SPICE for ESD circuit simulation. The key components relevant to ESD in the MOS model are studied and the implementation procedure is discussed. Experimental data measured from the human body model tester are included in support of the model.

Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications

Our understanding on a silicon chip is limited due to low measurement resolution or model-silicon miscorrelation including variations. This paper shows that chips are better understood by combining noisy measurement results and model information through a mathematical algorithm. Our proposed method learns segment delays in logic circuits from quantized path delay measurements using ridge regression. During the learning process, we take advantage of both nominal segment delays and the delay sensitivity with respect to variations. We also interpret the ridge regression in Bayesian context and in doing so, propose an analytic formula to set the regularization parameter of the ridge regression. For the silicon measurement environments where low measurement resolution is the dominant source of measurement noise, this formula allows us to predict post-silicon results more accurately and speed up the algorithm eliminating inefficient and inaccurate cross-validation. We also demonstrate our method in enhancing the resolution of already measured path delays. We learn segment delays from quantized path delay measurements and predict the path delays prior to the quantization. Our simulation results show that the predicted path delays are much closer to actual values than the measured values and the nominal values.

Segment Delay Learning From Quantized Path Delay Measurements

Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with technology scaling, domino circuits are increasingly susceptible to switch failures due to various noise sources that include crosstalk, charge sharing and leakage. To test for such failures in a manufactured chip, we describe a test pattern generation methodology that generates specific test patterns to target such failures. These test patterns activate noise from multiple sources such that their combined effect causes a switch failure at a domino gate output. In addition, the test patterns propagate the resulting error to an observable output within the duration of the circuit's clock cycle. The methodology has been implemented and validated using a domino multiplier circuit.

/pdf/atpg-for-noise-induced-switch-failures-in-domino-logic-53ludzhuk0.pdf

ATPG for Noise-Induced Switch Failures in Domino Logic

In this paper, we propose a method for testing CMOS domino circuits using the transient power supply current. The method is based on monitoring and processing the transient current. We evaluate the effectiveness of this testing method through simulations of various domino circuits of different sizes. Moreover, we propose a normalising technique to mask the process variations effect associated with current testing. Furthermore, we present a test vector generation algorithm for testing large domino circuits, and develop and implement a clustering technique to improve the fault coverage of the test method when used with large circuits. The clustering algorithm divides the circuit into different clusters where each cluster is fed by a different power supply branch.

Dynamic current testing for CMOS domino circuits

Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. In this paper, we address the charge sharing noise issue. Specifically, we develop an accurate but tractable model for analyzing charge sharing that avoids costly Hspice simulations. The model is used to generate test vectors using a generalized ATPG tool. The charge-sharing model and the corresponding tests were validated using Hspice simulations on industrial circuits and it was also demonstrated that test vectors that establish high amounts of charge sharing could be generated for most domino gates.

Testing of dynamic logic circuits based on charge sharing

Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. The authors address the charge-sharing noise issue. Specifically, they develop an accurate but tractable model for analyzing charge sharing that avoids costly Hspice simulations. The model is used to generate test vectors using a generalized ATPG tool. The charge-sharing model and the corresponding tests are validated using Hspice simulations on industrial circuits and it is also demonstrated that test vectors that establish high amounts of charge sharing could be generated for most domino gates.

Test vector generation for charge sharing failures in dynamic logic

In this paper we analyze the coverage of distributed delay defects, on untested but functionally sensitizable paths, achieved by robustly testing a subset of paths in the circuit. This is measured by translating the information gained from robust testing into a set of linear constraints on edge delays and then using these to bound the circuit delay. Surprisingly, the results of our experiments on ISCAS benchmark circuits show that robust testing of a subset of paths in the circuit, may not cover distributed delay defects on the remaining paths very well at all.

Robust testing a subset of paths - untested paths in the circuit

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Testing of dynamic logic circuits based on charge sharing

Test vector generation for charge sharing failures in dynamic logic

Robust testing a subset of paths - untested paths in the circuit