M. J. Wolf
Fraunhofer Society
14 Papers
101 Citations
M. J. Wolf is an academic researcher from Fraunhofer Society. The author has contributed to research in topics: Wafer-level packaging & Redistribution layer. The author has an hindex of 7, co-authored 12 publications.
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Papers
Through silicon via technology — processes and reliability for wafer-level 3D system integration
Peter Ramm,M. J. Wolf,Armin Klumpp,Robert Wieland,Bernhard Wunderle,Bruno Michel,Herbert Reichl +6 more
- 27 May 2008
TL;DR: The ICV-SLID fabrication process is well suited for the cost-effective production of both, high-performance applications (e.g. 3D microprocessor) and highly miniaturized multi-functional systems as mentioned in this paper.
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High aspect ratio TSV copper filling with different seed layers
M. J. Wolf,T. Dretschkow,Bernhard Wunderle,N. Jurgensen,G. Engelmann,Oswin Ehrmann,Albrecht Uhlig,Bruno Michel,Herbert Reichl +8 more
- 27 May 2008
TL;DR: In this paper, through silicon via (TSV) filling using electrochemical deposition (ECD) of copper was discussed with respect to via diameter and via depth, and the impact of seed layer nature on filling ratio and void formation was discussed.
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Fabrication of Application Specific Integrated Passive Devices Using Wafer Level Packaging Technologies
Kai Zoschke,M. J. Wolf,Michael Topper,Oswin Ehrmann,T. Fritzsch,K. Kaletta,F.-J. Schmuckle,Herbert Reichl +7 more
TL;DR: In this article, the fabrication of integrated passive devices (IPDs) using wafer level thin film fabrication is discussed, and a brief overview of the different possibilities for the realization of IPDs using Wafer level packaging technologies is presented.
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Evaluation of thin wafer processing using a temporary wafer handling system as key technology for 3D system integration
Kai Zoschke,Matthias Wegner,Martin Wilke,N. Jurgensen,Christina Lopper,I. Kuna,V. Glaw,J. Roder,O. Wunsch,M. J. Wolf,Oswin Ehrmann,Herbert Reichl +11 more
- 01 Jun 2010
TL;DR: In this article, the authors describe the process integration of a temporary wafer handling system for wafer thinning and thin wafer backside processing, which is a key technology and enabler for the wafer level fabrication of through silicon via (TSV) based 3D architectures.
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3D image sensor SiP with TSV silicon interposer
I. Limansyah,M. J. Wolf,Armin Klumpp,Kai Zoschke,Robert Wieland,M. Klein,Hermann Oppermann,L. Nebrich,Andy Heinig,A. Pechlaner,Herbert Reichl,W. Weber +11 more
- 26 May 2009
TL;DR: In this article, a specific 3D image sensor system for automotive applications is presented based on wafer level technology using silicon interposer with Through Silicon Vias (TSV's), a flip chip assembled sensor element and a microcontroller.
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