The upgrade of the ATLAS experiment at LHC foresees the insertion of an innermost silicon layer, called the Insertable B-layer (IBL). The IBL read-out system will be equipped with new electronics. The Readout-Driver card (ROD) is a VME board devoted to data processing, configuration and control. A pre-production batch has been delivered for testing with instrumented slices of the overall acquisition chain, aiming to finalize strategies for system commissioning. In this paper system setups and results will be described, as well as preliminary studies on changes needed to adopt the ROD for the ATLAS Pixel Layers 1 and 2.

https://iopscience.iop.org/article/10.1088/1748-0221/9/01/C01044/pdf

``The Read-Out Driver'' ROD card for the Insertable B-layer (IBL) detector of the ATLAS experiment: commissioning and upgrade studies for the Pixel Layers 1 and 2

The incoming and future upgrades of LHC will require better performance by the data acquisition system, especially in terms of throughput due to the higher luminosity that is expected. For this reason, during the first shutdown of the LHC collider in 2013/14, the ATLAS Pixel Detector has been equipped with a fourth layer— the Insertable B-Layer or IBL—located at a radius smaller than the present three layers. To read out the new layer of pixels, with a smaller pixel size with respect to the other outer layers, a front end ASIC (FE-I4) was designed as well as a new off-detector read-out chain. The latter, accordingly to the structure of the other layers of pixels, is composed mainly of two 9U-VME read-out off-detector cards called the Back-Of-Crate (BOC) and Read-Out Driver (ROD). The ROD is used for data and event formatting and for configuration and control of the overall read-out electronics. After some prototyping samples were completed, a pre-production batch of 5 ROD cards was delivered with the final layout. Another production of 15 ROD cards was done in Fall 2013, and commissioning was completed in 2014. Altogether 14 cards are necessary for the 14 staves of the IBL detector, one additional card is required by the Diamond Beam Monitor (DBM), and additional spare ROD cards were produced for a total initial batch of 20 boards. This paper describes some integration tests that were performed and our plan to install the new DAQ chain for the layer 2, which is the outermost, and layer 1, which is external to the B-layer. This latter is the only layer that will not be upgraded to a higher readout speed. Rather, it will be switched off in the near future as it has too many damaged sensors that were not possible to rework. To do that, slices of the IBL read-out chain have been instrumented, and ROD performance is verified on a test bench mimicking a small-sized final setup. Thus, this contribution reports also how the adoption of the IBL ROD for ATLAS Pixel Detector Layer 2 was developed, with the production of other 40 boards completed and tested in 2015, and how the same approach will be used for the production of the last 45 ROD boards for the Layer 1. This latter fabrication has started on Fall 2015.

ATLAS Pixel Detector ROD card from IBL towards Layers 2 and 1

The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called the Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL's off-detector DAQ system. The strategy for IBL ROD firmware development was three-fold: keeping as much of the Pixel ROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware, and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ test bench using a realistic front-end chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data path implementation, test on the test bench and ROD prototypes, will be reported. Recent Pixel collaboration efforts focus on finalizing hardware and firmware tests for the IBL. The plan is to approach a complete IBL DAQ hardware-software installation by the end of 2014.

https://iopscience.iop.org/article/10.1088/1748-0221/10/03/C03037/pdf

Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

This paper presents a sensorized belt with four fully integrated pressure-touch sensors. We propose a very-low complexity sensor able to measure a pressure variation (up to 4 MPa) and to identify with accuracy a contact event at around 10 kPa. The overall pressure/touch sensor integrates a transducer, based on piezo capacitive material, coupled with a read-out circuit designed around a ring-oscillator. This converts the capacitance variation of the transducer into a quasi-digital signal characterized by a frequency range of 36.3–270 kHz with a very low standard deviation (2.3 kHz) and a sensitivity of 2.2 Hz/Pa. The tight integration of the electronics with the transducer results in a very compact all-in-one sensor system (overall size is 20 mm × 20 mm × 10 mm). Further, a major benefit of a low complexity design is the low power consumption, measured to be ∼370 μW. Based on a quasi-digital approach (event-driven), the system is well suited for impulse-based wireless communication.

A quasi-digital pressure/touch sensor prototype for orbital targets contact event monitoring

The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back-compatible solution (using a Digital Signal Processor) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported.

/pdf/implementation-and-tests-of-fpga-embedded-powerpc-in-the-593q7uwu39.pdf

Implementation and tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card

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Implementation and tests of FPGA-embedded PowerPC in the control system of the ATLAS IBL ROD card