This paper describes the Design for Test (DFT) and silicon debug features of the Pentium(R) Pro processor, and its production test development methodology. The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing with low defect rates led the design team to a custom low-area DFT approach, coupled with a manually-written test methodology which targeted several fault models. Results show that this approach was effective in balancing testability needs with other design constraints, while enabling excellent time to market and test quality.

Pentium(R) Pro processor design for test and debug

The complexity of today's hundreds-of-million-transistor microprocessors all but guarantees imperfect first silicon, but leaves unanswered the question of what exactly will go wrong. This article describes features added to the cell broadband engine processor to enable debugging in the presence of such unknown events.

Cell Broadband Engine Debugging for Unknown Events

The need to quickly ramp a complex, high-performance microprocessor into high-volume manufacturing with low defect rates led this design team to a custom, low-area DFT approach and a manually written test methodology that targeted several fault models. Their approach effectively balanced testability needs with other design constraints, while enabling excellent time to market and test quality.

Pentium Pro processor design for test and debug

An Efficient Exact Algorithm for Constraint Bipartite Vertex Cover

This paper presents the testing methodology of the UltraSPARC T1 microprocessor and the challenges to productizing the industry's first 8 cores and 32 thread microprocessor. The challenges include effectively testing 8 individual cores that share common functional blocks (L2 cache, cache crossbar, floating point unit), reducing 8times conventional production test time and tester memory while achieving the same coverage, and productizing 6 core or 8 core devices at the targeted frequency. Highlights of DFT features designed to overcome the challenges are presented followed by a production flow together with key learning and future improvement plans

Testing of UltraSPARC T1 Microprocessor and its Challenges

With a focus on a short time to volume production, the UltraSparc microprocessor design incorporated innovative features that optimize test, debug and manufacture. The following areas are discussed: goals; cost-benefit analysis; scan design; decoded multiplexer; test generation flow; custom circuit blocks; boundary cell design; embedded array testing; and clock control features.

Designing UltraSparc for testability

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Designing UltraSparc for testability