Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an in-depth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logical, and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.

/pdf/power-minimization-in-ic-design-principles-and-applications-4l53tahw7t.pdf

Power minimization in IC design: principles and applications

Typical address-oriented computer memories cannot recognize incomplete or noisy information. Associative (content-addressable) memories solve this problem but suﬀer from severe capacity shortages. I propose a model of a quantum memory that solves both problems. The storage capacity is exponential in the number of qbits and thus optimal. The retrieval mechanism for incomplete or noisy inputs is probabilistic, with postselection of the measurement result. The output is determined by a probability distribution on the memory which is peaked around the stored patterns closest in Hamming distance to the input.

Probabilistic Reliable Dissemination in Large-Scale Systems

Power consumption is rapidly becoming an area of growing concern in IC and system design houses. Issues such as battery life, thermal limits, packaging constraints and cooling options are becoming key factors in the success of a product. As a consequence, IC and system designers are beginning to see the impact of power on design area, design speed, design complexity and manufacturing cost. While process and voltage scaling can achieve significant power reductions, these are expensive strategies that require industry momentum, that only pay off in the long run. Technology independent gains for power come from the area of design for low power which has a much higher return on investment (ROI). But low power design is not only a new area but is also a complex endeavour requiring a broad range of synergistic capabilities from architecture/microarchitecture design to package design. It changes traditional IC design from a two-dimensional problem (Area/performance) to a three-dimensional one (Area/Performance/Power). This paper describes the CAD tools and methodologies required to effect efficient design for low power. It is targeted to a wide audience and tries to convey an understanding of the breadth of the problem. It explains the state of the art in CAD tools and methodologies. The paper is written in the form of a tutorial, making it easy to read by keeping the technical depth to a minimum while supplying a wealth of technical references. Simultaneously the paper identifies unresolved problems in an attempt to incite research in these areas. Finally an attempt is made to provide commercial CAD tool vendors with an understanding of the needs and time frames for new CAD tools supporting low power design. >

/pdf/power-conscious-cad-tools-and-methodologies-a-perspective-5f06ec9yt2.pdf

Power conscious CAD tools and methodologies: a perspective

In this paper we propose a very-low-voltage (VLV) testing technique for CMOS logic ICs. Voltage dependence of CMOS logic circuit operation in the presence of resistive shorts and hot carrier damage is studied. It is shown that at certain much-lower-than-normal power supply voltage, weak CMOS logic ICs due to the presence of these flaws can be forced to malfunction while truly good ICs continue to function. Very-low-voltage testing also detects pattern dependent faults caused by resistive shorts. Because of its simplicity and because there is no overhead associated with it, very-low-voltage testing can easily be applied to chips and circuit boards as a production test, field test, or failure diagnosis technique. >

Very-low-voltage testing for weak CMOS logic ICs

In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I/sub gate/. We find that for technologies with appreciable I/sub gate/, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I/sub sub/ reduction.

/pdf/gate-oxide-leakage-current-analysis-and-reduction-for-vlsi-32fxe0e1wo.pdf

Gate oxide leakage current analysis and reduction for VLSI circuits

Two methods for the calculation of node signal probabilities in combinational networks are presented. These techniques provide a better accuracy than existing algorithms and a deeper insight in the effects of first-order correlations due to multiple fan-out reconvergences. The proposed algorithms are shown to compare favorably with existing procedures in the analysis of significant benchmarks, both in accuracy and in computational efficiency. >

Estimate of signal probability in combinational logic networks

An investigation of the properties of multiple input shift registers for signature analysis is presented. The assumption of independent errors at the register inputs has been used to model the register behavior as a Markov process whose equations have been solved to obtain the exact dependence of aliasing probabilities as a function of test length, input error probabilities, and feedback structure. Some unique featured of maximum-length registers are proven. Accurate simplified expressions of aliasing probability are derived for use as tools in the evaluation of the coverage. >

Aliasing in signature analysis testing with multiple input shift registers

The authors present ideas for addressing the problem of detecting non-stuck-at faults in CMOS circuits that cannot be revealed by means of conventional methods (i.e., as logical errors in the steady-state response). Two techniques are proposed for detecting analog faults, particularly those resulting in intermediate voltages along circuit branches due to faulty conductive paths between the power supply and ground. Involving the conversion of analog faults into stuck-ats and the use of distributed testing logic, these techniques are shown to avoid the drawbacks of previous solutions. A method is proposed for online detection of delay faults, so far not yet considered in the context of design-for-testability. All the proposed techniques require little extra hardware and lead to minimal performance degradations. >

Novel design for testability schemes for CMOS ICs

Signature analysis with multiple-input shift registers (MISRs) is often used to realize efficient built-in self-test of digital VLSI circuits. The authors present a statistical theory that explains the dependence of aliasing probability on the main MISR features, such as length and feedback network, and thus makes it possible to prove criteria for the MISR design. The assumption of independent errors at the register inputs is used to model the register behavior as a Markov process, whose equations are then solved to obtain the exact dependence of aliasing probability as a function of test length, input error probabilities, and feedback structure. >

Aliasing in signature analysis testing with multiple-input shift-registers

The authors present a novel technique to study the detection of non-stuck-at faults in CMOS circuits. Gate-level models of CMOS faults not yet adequately covered in the literature are developed. Suitable models for transistor stuck-open and stuck-on, gate-drain shorts, and bridgings are implemented in a fault simulator. Results obtained with typical circuits are presented and discussed to analyze the influence of circuit architecture and type of test vector (deterministic or pseudorandom) on the coverage of non-stuck-at faults. The following general conclusions are drawn from these results: (1) shorts between transistor gate and drain are adequately detected by stuck-at oriented test patterns, and, hence, they do not represent a significant problem in IC testing: (2) the coverage of transistors stuck-open is significantly dependent on the test pattern generation method used; (3) the detectability of bridgings depends strongly on the circuit topology; and (4) the indirect coverage of transistors stuck-on is inadequate, essentially because a large number of them are undetectable. >

Fault simulation of unconventional faults in CMOS circuits

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