M. Cruz
SEMATECH
6 Papers
67 Citations
M. Cruz is an academic researcher from SEMATECH. The author has contributed to research in topics: CMOS & Metal gate. The author has an hindex of 5, co-authored 6 publications.
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Papers
Growth mechanism of TiN film on dielectric films and the effects on the work function
Kisik Choi,Patrick S. Lysaght,Husam N. Alshareef,Craig Huffman,Huang-Chun Wen,R. Harris,H. Luan,P. Y. Hung,Chris M. Sparks,M. Cruz,Ken Matthews,Prashant Majhi,Byoung Hun Lee +12 more
TL;DR: In this article, the growth mechanism of ALD-TiN film on different dielectrics and the resulting effective work function value was investigated and the growth rate and nucleation rate were found to be dependent on the dielectric films.
47
•Proceedings Article
Gate first high-k/metal gate stacks with zero SiO x interface achieving EOT=0.59nm for 16nm application
Jiacheng Huang,Dawei Heh,Prasanna Sivasubramani,Paul Kirsch,Gennadi Bersuker,David Gilmer,Manuel Quevedo-Lopez,Muhammad Mustafa Hussain,Prashant Majhi,P. Lysaght,Hokyung Park,Niti Goel,Chadwin D. Young,Chanro Park,C. Park,M. Cruz,V. Diaz,P. Y. Hung,J. Price,H.-H. Tseng,Raj Jammy +20 more
- 01 Jun 2006
TL;DR: Gate first 0.59 nm EOT HfOx/metal gate stacks for 16 nm node application are demonstrated for the first time and the improved scalability of ZIL H fO x vs. exotic higher-k is compared and demonstrated.
41
Dual channel FinFETs as a single high-k/metal gate solution beyond 22nm node
Casey Smith,Hemant Adhikari,S-H. Lee,Brian Coss,Srivatsan Parthasarathy,Chadwin D. Young,B. Sassman,M. Cruz,Chris Hobbs,Prashant Majhi,Paul Kirsch,R. Jammy +11 more
- 01 Dec 2009
TL;DR: In this paper, dual channel materials using FinFETs for high-performance CMOS for sub 22 nm technology node were reported, which exhibit 3.6X hole mobility enhancement over Silicon (100) while allowing for V TH control with single high-k and metal gate stack.
20
Challenges of III–V materials in advanced CMOS logic
Paul Kirsch,Hill Richard J,Jiacheng Huang,Wei-Yip Loh,Tae-Woo Kim,Man Hoi Wong,B.-G. Min,Craig Huffman,Dmitry Veksler,Chadwin D. Young,K.-W. Ang,I. Ali,Rinus T. P. Lee,T. Ngai,A. Wang,W.-E Wang,T.H. Cunningham,Y.T. Chen,P. Y. Hung,E. Bersch,B. Sassman,M. Cruz,S. Trammell,Ravi Droopad,S. Oktybrysky,J.C. Lee,Gennadi Bersuker,Chris Hobbs,R. Jammy +28 more
- 23 Apr 2012
TL;DR: This paper examines the module challenges of III-V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj;60;10nm.
5
•Proceedings Article
A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications
Chanro Park,Muhammad Mustafa Hussain,Jiacheng Huang,C. Park,K. Tateiwa,Chadwin D. Young,Hokyung Park,M. Cruz,David Gilmer,K. Rader,J. Price,P. Lysaght,Dawei Heh,Gennadi Bersuker,Paul Kirsch,H.-H. Tseng,Raj Jammy +16 more
- 01 Jun 2006
TL;DR: In this article, a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32 nm LSTP applications is presented.
5