Real-time operating systems are an integral part of complex real-time systems. Three general categories of real-time operating systems exist: small, proprietary kernels, real-time extensions to commercial timesharing operating systems, and research kernels. This paper discusses each of these areas focusing on how each of these classes deal with predictability. It is argued that the small, proprietary kernels are predictable, but offer little help to the real-time systems designer and implementor in producing predictable applications. Real-time versions of commercial operating systems like UNIX and Mach offer greater implementation support, but are, in general, NOT predictable themselves nor offer enough support to applications which require predictability. This, of course, does not mean that there is no way to achieve predictability with these operating systems. It is possible to achieve predictability by very careful design, by using a very limited subset of the overall features provided, and by proving that the features being used for predictability cannot in any way be impacted by any other part of the system. Finally, research kernels are attempting to provide greater design, implementation and evaluation support together with predictability for both the operating system and the application.

Real-Time Operating Systems

Sparse and irregular computations constitute a large fraction of applications in the data-intensive scientific domain. While every effort is made to balance the computational workload in such computations across parallel processors, achieving sustained near machine-peak performance with close-to-ideal load balanced computation-to-processor mapping is inherently difficult. As a result, most of the time, the loads assigned to parallel processors can exhibit significant variations. While there have been numerous past efforts that study this imbalance from the performance viewpoint, to our knowledge, no prior study has considered exploiting the imbalance for reducing power consumption during execution. Power consumption in large-scale clusters of workstations is becoming a critical issue as noted by several recent research papers from both industry and academia. Focusing on sparse matrix computations in which underlying parallel computations and data dependencies can be represented by trees, this paper proposes schemes that save power through voltage/frequency scaling. Our goal is to reduce overall energy consumption by scaling the voltages/frequencies of those processors that are not in the critical path; i.e., our approach is oriented towards saving power without incurring performance penalties.

Reducing power with performance constraints for parallel sparse applications

Reducing device energy has become one of the most important challenges to embedded systems designers. Processors with dynamic voltage scaling permit trading performance for reduced energy consumption as a program executes. In this paper, we first present a novel hybrid scheme that uses dynamic voltage scaling to adjust the performance of embedded applications to reduce energy consumption while also meeting time constraints. Our fine grained approach uses the compiler to insert power management hints in the application code. These hints convey path specific run-time information about the program's progress to power management points invoked by the operating system that adjust processor performance. Second we present an algorithm for inserting power management hints along different program paths. Finally, we experimentally evaluate our approach and show that signi cant energy reduction can be achieved. On two embedded applications, MPEG movie decoding and automatic target recognition, our scheme reduces energy by up to 79% over no power management and by up to over 50% static power management. We also experimentally demonstrate that our scheme achieves more energy savings compared to two purely compiler directed schemes.

/pdf/energy-management-for-real-time-embedded-applications-with-4xqbm52tkq.pdf

Energy management for real-time embedded applications with compiler support

Static timing analysis safely bounds worst-case execution times to determine if tasks can meet their deadlines in hard real-time systems. However, conventional timing analysis requires that the upper bound of loops be known statically, which limits its applicability. Parametric timing analysis methods remove this constraint by providing the WCET as a formula parameterized on loop bounds. This paper contributes a novel technique to allow parametric timing analysis to interact with dynamic real-time schedulers. By dynamically detecting actual loop bounds, a lower WCET bound can be calculated, on-the-fly, for the remaining execution of a task. We analyze the benefits from parametric analysis in terms of dynamically discovered slack in a schedule. We then assess the potential for dynamic power conservation by exploiting parametric loop bounds for ParaScale, our intra-task dynamic voltage scaling (DVS) approach. Our results demonstrate that the parametric approach to timing analysis provides 66%-80% additional savings in power consumption. We further show that using this approach combined with online intra-task DVS to exploit parametric execution times results in much lower power consumption. Hence, even in the absence of dynamic scheduling, significant savings in power can be obtained, e.g., in the case of cyclic executives

/pdf/parascale-exploiting-parametric-timing-analysis-for-real-3xkhqj3xys.pdf

ParaScale: exploiting parametric timing analysis for real-time schedulers and dynamic voltage scaling

https://academic.csuohio.edu/yuc/papers/JSA_DVS.pdf

Dynamic voltage scaling techniques for power efficient video decoding

Managing energy consumption has become vitally important to battery operated portable and embedded systems. A dynamic voltage scaling (DVS) technique reduces the processor's dynamic power consumption quadratically at the expense of linearly decreasing the performance. Reducing energy using DVS in the context of real-time systems should consider this tradeoff. In this paper we introduce a novel collaborative approach between the compiler and the operating system (OS) that uses fine-grained information about the execution times of a real-time application to reduce energy consumption. We use the compiler to annotate an application's source code with path-dependent information called power management hints (PMHs). This information captures the temporal behavior of the application, which varies by executing different paths. During program execution, the OS periodically changes the processor's frequency and voltage based on the temporal information provided by the PMHs. These speed adaptation points are called power management points (PMPs). We evaluate our scheme using two embedded applications: a video decoder and an automatic target recognition application. Our scheme shows an energy reduction of up to 79% over no power management and up to 50% over a static power management scheme.

/pdf/collaborative-operating-system-and-compiler-power-management-46sfbfakt3.pdf

Collaborative operating system and compiler power management for real-time applications

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Collaborative operating system and compiler power management for real-time applications